10.12. Intel® HLS Compiler Standard Edition Streaming Input Interfaces
Use the stream_in object and template arguments to explicitly declare Avalon® Streaming (ST) input interfaces. You can also use the stream_in Function APIs.
| Template Object or Argument | Description |
|---|---|
| ihc::stream_in | Streaming input interface to the component. |
| ihc::buffer | Specifies the capacity (in words) of the FIFO buffer on the input data that associates with the stream. |
| ihc::readyLatency | Specifies the number of cycles between when the ready signal is deasserted and when the input stream can no longer accept new inputs. |
| ihc::bitsPerSymbol | Describes how the data is broken into symbols on the data bus. |
| ihc::usesPackets | Exposes the startofpacket and endofpacket sideband signals on the stream interface. |
| ihc::usesValid | Controls whether a valid signal is present on the stream interface. |
ihc::stream_in Template Object
- Syntax
- ihc::stream_in<datatype, template arguments >
- Valid Values
- Any valid C++ datatype
- Default Value
- N/A
- Description
-
Streaming input interface to the component.
The width of the stream data bus is equal to a width of sizeof(datatype).
The testbench must populate this buffer (stream) fully before the component can start to read from the buffer.
To learn more, review the following tutorials:- <quartus_installdir>/hls/examples/tutorials/interfaces/explicit_streams_buffer
- <quartus_installdir>/hls/examples/tutorials/interfaces/explicit_streams_packet_ready_valid
- <quartus_installdir>/hls/examples/tutorials/interfaces/mulitple_stream_call_sites
ihc::buffer Template Argument
- Syntax
- ihc::buffer<value>
- Valid Values
- Non-negative integer value.
- Default Value
- 0
- Description
-
The capacity, in words, of the FIFO buffer on the input data that associates with the stream. The buffer has latency. It immediately consumes data, but this data is not immediately available to the logic in the component.
If you use the tryRead() function to access this stream and the stream read is scheduled within the first cycles of operation, the first (or more) calls to the tryRead() function might return false in co-simulation (and therefore in hardware).
This parameter is available only on input streams.
ihc::readyLatency Template Argument
- Syntax
- ihc::readylatency<value>
- Valid Values
- Non-negative integer value between 0-8.
- Default Value
- 0
- Description
- The number of cycles between when the ready signal is deasserted and when the input stream can no longer accept new inputs.
ihc::bitsPerSymbol Template Argument
- Syntax
- ihc::bitsPerSymbol<value>
- Valid Values
- A positive integer value that evenly divides by the data type size.
- Default Value
- Datatype size
- Description
-
Describes how the data is broken into symbols on the data bus.
Data is always broken down in little endian order.
ihc::usesPackets Template Argument
- Syntax
- ihc::usesPackets<value>
- Valid Values
- true or false
- Default Value
- false
- Description
- Exposes the startofpacket and endofpacket sideband signals on the stream interface, which can be accessed by the packet based reads/writes.
ihc::usesValid Template Argument
- Syntax
- ihc::usesValid<value>
- Valid Values
- true or false
- Default Value
- true
- Description
-
Controls whether a valid signal is present on the stream interface. If false, the upstream source must provide valid data on every cycle that ready is asserted.
This is equivalent to changing the stream read calls to tryRead and assuming that success is always true.
If set to false, buffer and readyLatency must be 0.
Intel® HLS Compiler Standard Edition Streaming Input Interface stream_in Function APIs
| Function API | Description |
|---|---|
| T read() | Blocking read call to be used from within the component |
| T read(bool& sop, bool& eop) | Available only if usesPackets<true> is set. Blocking read with out-of-band startofpacket and endofpacket signals. |
| T tryRead(bool &success) | Non-blocking read call to be used from within the component. The success bool is set to true if the read was valid. That is, the Avalon® -ST valid signal was high when the component tried to read from the stream. The emulation model of tryRead() is not cycle-accurate, so the behavior of tryRead() might differ between emulation and co-simulation. |
| T tryRead(bool& success, bool& sop, bool& eop) | Available only if usesPackets<true> is set. Non-blocking read with out-of-band startofpacket and endofpacket signals. |
| void write(T data) | Blocking write call to be used from the testbench to populate the FIFO to be sent to the component. |
| void write(T data, bool sop, bool eop) | Available only if usesPackets<true> is set. Blocking write call with out-of-band startofpacket and endofpacket signals. |
Intel® HLS Compiler Streaming Input Interfaces Code Example
The following code example illustrates both stream_in declarations and stream_in function APIs.
// Blocking read
void foo (ihc::stream_in<int> &a) {
int x = a.read();
}
// Non-blocking read
void foo_nb (ihc::stream_in<int> &a) {
bool success = false;
int x = a.tryRead(success);
if (success) {
// x is valid
}
}
int main() {
ihc::stream_in<int> a;
ihc::stream_in<int> b;
for (int i = 0; i < 10; i++) {
a.write(i);
b.write(i);
}
foo(a);
foo_nb(b);
}