F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 7/06/2024
Public
Document Table of Contents

3.9. Deterministic Latency

When the Deterministic Latency (DL) option is selected in the F-Tile Serial Lite IV Intel® FPGA IP, the following main components supporting the DL solution will be included in the design example:
  • SYSREF Pulse Generator
  • TX DL shim wrapper
  • RX DL shim wrapper
Note: Deterministic Latency value = latency between TX DL SHIM input (from USR_IF) and RX DL SHIM output (to USR_IF).
Figure 22.  F-Tile Serial Lite IV DL Example Design Diagram