F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

2.3.1. Design Example Parameters

The F-Tile Serial Lite IV Intel® FPGA IP parameter editor includes an Example Design tab for you to specify parameters before generating the design example.
Figure 4. Example Design Tab
Table 4.  Parameters in the Example Design Tab
Parameter Description
Generate Files for

The IP generates the necessary design example files for simulation and compilation.

Simulation—select this option to generate the necessary design simulation files.

Synthesis—select this option to generate the necessary design synthesis files. Use these files to compile the design in the Quartus® Prime Pro Edition software for hardware testing.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.
Select Board Supported hardware for design implementation. When you select an Intel FPGA development board, the Target Device is the one that matches the device on the Development Kit.

If this menu is grayed out, there is no supported board for the options that you select.

Agilex™ 7 I-Series Transceiver-SoC Development Kit: This option allows you to test the design example on the selected Agilex™ 7 I-Series Transceiver-SoC development kit.
Note: This option is only available when your target device is:
  • AGIB027R31B1E2V for FHT
  • AGIB027R31B2E2V for FGT

No Development Kit: This option excludes the hardware aspects for the design example.

Change Target Device Select a different device grade for Intel® FPGA IP development kit. For device-specific details, refer to the device datasheet on the Intel FPGA website.
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