F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 7/06/2024
Public
Document Table of Contents

3.7.1. Setting Up and Running the Toolkit

To enable the F-Tile Serial Lite IV IP toolkit, you must download and run the toolkit.
To run the toolkit, follow these steps:
  1. Generate the design example after you specify the parameters.
  2. Compile the design example to generate a .sof file.
  3. In the Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  4. In the system console, click Load Design and select the .sof file for the design example.
  5. Under the list of Instances, select sliv_ip_toolkit_1.0 of seriallite_iv_streaming_inst.
  6. Under the Details pane, select F-Tile Serial Lite IV IP Toolkit and click Open Toolkit to launch the toolkit.
    Figure 14. Launch the F-Tile Serial Lite IV IP Toolkit
When the toolkit is up and running, set JTAG master by following the instructions given in the display window.
Figure 15. Setting JTAG Master
Note: Set to JTAG master phy_jtag_m.master for MAC and PCS Tab and demo_jtag_m.master for GUI configuration and Traffic statistics tab.