F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

Download PDF
ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.
  1. Change the working directory to <example_design_directory>/ed_sim.
  2. Run the simulation script for the simulator of your choice.
    Table 6.  Testbench Simulation Scripts
    Simulator File Directory Command
    ModelSim* <variation name>sl4_f_0_example_design/ed_sim source run_mentor.tcl
    Note: source evaluates a file or resource as a Tcl script (Tools - Tcl - Execute - Macro).
    QuestaSim*
    VCS* <variation name>sl4_f_0_example_design/ed_sim sh run_vcs.sh
    VCS* MX <variation name>sl4_f_0_example_design/ed_sim sh run_vcsmx.sh
    Xcelium* <variation name>sl4_f_0_example_design/ed_sim sh run_xcelium.sh
    Riviera-PRO* <variation name>sl4_f_0_example_design/ed_sim riviera -do run_riviera.do
  3. When the simulation is complete, you can now analyze the results and verify the design. A successful simulation ends with the following message, "Test Passed." 
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 534579600
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 0
#    
#    Random number generator seed   = 1756255697
#    
#    Link Latency                   = 434 ns
#    
#    *************************************** Test Passed **************************************
Level Two Title