F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 7/06/2024
Public
Document Table of Contents

3.3. Simulation

Figure 8.  Example Testbench (Duplex) for Agilex™ 7 F-Tile Devices

The simulation test cases demonstrate streaming of 10,000 sample words from the traffic generator to the F-Tile Serial Lite IV TX core, and externally loopback to the RX core. The words are either separated into different bursts or continuously transferred in a single burst. The transfer modes are randomized by the testbench.

The simulation test case performs the following steps:
  1. Initializes and configures F-Tile Serial Lite IV Intel® FPGA IP, traffic generator, and traffic checker.
  2. Traffic generator generates data and starts data transmission.
  3. Logs and displays link up status and burst information.
  4. Traffic checker verifies received data and stops transmission.
  5. Testbench logs and displays test results and test information.