F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.4. Hardware Testing

The hardware design example provides the loopback test. In loopback test mode, the traffic generator sends packets to the F-Tile Serial Lite IV TX core and loopback to the RX core either internally or externally.

Figure 9. Loopback Test

To use the system console script, navigate to the ./ed_hwtest/system_console directory. Source the sliv_ftile.tcl script. The system console script provides useful commands for reading statistics and enables you to control various features in the design.

Table 12.  System Console Commands for Hardware Testing
Command Function
list_jtag Displays a list of JTAG master indexes that are connected to your board.
set_jtag <jtag master_index number> Selects the JTAG master.
  • To enable internal and external loopback, use the JTAG master index number of phy_1/phy_jtag_m JTAG node.
    For example, the JTAG master index of phy_1/phy_jtag_m JTAG node shown in the following JTAG list is 2. Type set_jtag 2 to select JTAG master index 2. Next type the enable internal or external loopback commands. 
    % list_jtag
Available JTAG Masters:
0:    /devices/<JTAG_port>/phy_0/master
1:    /devices/<JTAG_port>/phy_0/demo_jtag_m.master
2:    /device/<JTAG_port>/phy_1/phy_jtag_m.master
  • To perform commands other than internal and external loopback, use JTAG master index number of phy_0/demo_jtag_m JTAG node.
    For example, the JTAG master index of phy_0/demo_jtag_m JTAG node shown in the following JTAG list is 1. Type set_jtag 1 to select JTAG master index 1. Next type the system console command that you want to use. 
    % list_jtag
Available JTAG Masters:
0:    /devices/<JTAG_port>/phy_0/master
1:    /devices/<JTAG_port>/phy_0/demo_jtag_m.master
2:    /device/<JTAG_port>/phy_1/phy_jtag_m.master
read_error_statistic Displays the error statistics.
sl4_link_init_int_lpbk <index number> Enables TX to RX internal serial loopback within the transceiver and performs the specific transceiver calibration flow.
  • 0: Disable internal serial loopback
  • 1: Enable internal serial loopback
traffic_gen_enable Enables the traffic generator and checker.
traffic_gen_disable Disables the traffic generator and checker.
continuous_mode_en Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate continuous (single continuous data generation) traffic stream.
burst_mode_en

Resets the TX and RX core (MAC and PHY) and enables the traffic generator to generate a burst (multiple burst packet data generation) traffic stream.

Not applicable for Deterministic Latency Enabled design.
crc_err_inject_pulse Enables CRC error injection for all lanes.
reconfig_tx_sel To access Avalon® memory-mapped interface through TX.
reconfig_rx_sel To access Avalon® memory-mapped interface through RX.
reg_write <avmm2_address> <desired_value> Perform write operation on reconfig_*/AVMM2 interface.
reg_read <avmm2_address> Perform read operation on reconfig_*/AVMM2 interface.
proc_avmm1_write <avmm1_address> <desired_value> Perform write operation on reconfig_sl_*/AVMM1 interface.
proc_avmm1_read <avmm1_address> Perform read operation on reconfig_sl_*/AVMM1 interface.
Figure 10. Steps to perform Hardware Testing
Figure 11. Example of Hardware Design Example Test Result in System Console
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