F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

2.5. Compiling and Testing the Design

Follow these steps to compile and test the design:

  1. Launch the Quartus® Prime Pro Edition software and change the directory to example_design_dir/ed_synth/ and open the seriallite_iv_streaming_demo.qpf file.
  2. Click Processing > Start Compilation to compile the design.

    The Quartus® Prime Pro Edition software automatically loads the timing constraints for the design example and the design components during compilation.

  3. Connect the development board to the host computer.
  4. Launch the Clock Control application, which is part of the development kit. Set new frequencies for the design example using the following configurations:
    • FGT designs
      • systempll_ref_clk: System PLL reference clock frequency
        Note: This clock is only available when the System PLL frequency selection is set to Custom
      • pll_ref_clk: PMA reference clock frequency
      • iopll_ref_clk: PMA reference clock frequency
      • mgmt_clk: 100 MHz
      Table 7.  Clock Pin Output for FGT Designs
      Clock PAM4 NRZ
      Number of PMA lanes >8 Number of PMA lanes ≤8
      systempll_ref_clk Si5391 (U45) -OUT5 Si5391 (U45) -OUT9A Si5391-A (U18) -OUT9
      pll_ref_clk Si5391 (U45) -OUT0 Si5391 (U45) -OUT1 Si5391-A (U18) -OUT5
      iopll_ref_clk Si5332 (U19) -OUT1
      mgmt_clk Si5332 (U19) -OUT6
    • FHT designs
      • pll_ref_clk: System PLL reference clock frequency
        Note: This signal is always available regardless of the System PLL frequency selection
      • pll_ref_clk_fht: PMA reference clock frequency
      • iopll_ref_clk: PMA reference clock frequency
      • mgmt_clk: 100 MHz
      Table 8.  Clock Pin Output for FHT Designs
      Clock PAM4 and NRZ
      pll_ref_clk Si5394 (U118) -OUT3
      pll_ref_clk_fht Si5394 (U118) -OUT1
      iopll_ref_clk Si5332 (U19) -OUT1
      mgmt_clk Si5332 (U19) -OUT6
    Note: Refer to the Agilex™ 7 I-Series Transceiver-SoC Development Kit User Guide for steps to program the clock oscillator on board.
  5. Configure the FPGA on the development board using the generated seriallite_iv_streaming_demo.sof file (Tools > Programmer).

    The design example targets the Agilex™ 7 I-Series Transceiver-SoC Development Kit.

    The design includes a Synopsys* Design Constraints File (.sdc) and an Quartus® Prime Pro Edition Settings File (.qsf) with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device settings and constraints in the .qsf file.

  6. After loading the .sof file onto the development board, run the hardware design example using either System Console or the F-Tile Serial Lite IV toolkit. For more information about the F-Tile Serial Lite IV IP toolkit, refer to the F-Tile Serial Lite IV IP Toolkit section.
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