F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.9.4. Deterministic Latency Design Considerations

The TX/RX core clock should be faster than the TX/RX user clock to overcome the inefficiency due to CW insertion and tx_ready de-assertion due to FEC_AM insertion and tx_ready deassertion events for BASIC mode.

For safety, a 10% margin between the user clock and core clock needs to be maintained to avoid any loss of data.

In summary, the following are the requirements that you must follow when the DL feature is enabled, which will have a deterministic latency value between user the TX data path and the user RX datapath:
  • F-Tile Serial Lite IV Intel® FPGA IP core clock should be ≥1.1 usrclk (user clock).
  • User clock for both TX and RX logic should be sourced from the same clock.
  • TX/RX DL shim wrapper user reset should be triggered whenever the F-Tile Serial Lite IV Intel® FPGA IP TX/RX core reset is triggered.
  • SYSREF_PERIOD parameter value of the SYSREF Pulse Generator is recommended to be set ≥1024 user clock cycles.
  • RBD value set should be greater than the latency of TX+RX (including TX DL shim and RX DL shim) in user_clk cycle + 13. There will be a maximum value before the DCFIFO within the RX DL module hits full. The default DCFIFO size of 64 is used in the example design.

  • Calibrate the RBD value per IP variant used to ensure that the RX DL DCFIFO will not hit the empty/full scenario, else the IP latency will no longer be deterministic and valid.

    For the generated SL4 example design, the recommended DL RBD requirement as shown (in user clock cycles):
    • 184 < RBD < 218
    Note: The RBD maximum value can be further increased by increasing the RX DL wrapper DCFIFO size manually.
Table 19.  Recommended Deterministic Latency RBD values
CRC Soft CWBIN Counters Latency (in TX user clock cycle) Recommended Minimum RBD Delay Value (avoid RX DCFIFO empty) Recommended Maximum RBD Delay Value (avoid RX DCFIFO full)
On On 172 185

217

213 (system PLL frequency > transceiver clock frequency)
Off On 162 175

207

203 (system PLL frequency > transceiver clock frequency)
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