F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.9.1. SYSREF Pulse Generator

This is a simple periodic pulse generator based on the TX/RX user clock (TX and RX user clocks should come from the same source). SYSREF generation would start after a START_DELAY value (in the user clock cycle) with the pulse generation at the rising edge of the user clock. SYSREF_PERIOD must be more than the F-Tile Serial Lite IV Intel® FPGA IP latency and the delay variation across lanes within a link, it should be selected to be at least 1024 sl4 tx_core_clk. The SYSREF_PERIOD parameter value is recommended to be set ≥1024. The START_DELAY and SYSREF_PERIOD user-programmable parameters are available in the design module.

Figure 23. SYSREF Pulse Generator Parameters
Table 16.  SYSREF Pulse Generator I/O Signals
Signal Name Direction Type Description
clk Input Wire Input clock from user clock source.
rst Input Wire Active high asynchronous reset to reset the pulse generator.
sysref Output Reg Periodic pulse signal for the TX DL wrapper, RX DL wrapper, and F-Tile Serial Lite IV Intel® FPGA IP core.
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