ASMI Parallel Intel® FPGA IP Core User Guide

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ID 683205
Date 7/02/2019
Public
Document Table of Contents
Document Table of Contents x
1. ASMI Parallel Intel® FPGA IP Core User Guide
1. ASMI Parallel Intel® FPGA IP Core User Guide x
1.1. Device Family Support 1.2. Ports and Parameters 1.3. Installing and Licensing Intel® FPGA IP Cores 1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements 1.5. ASMI Parallel Intel® FPGA IP Core User Guide Archives 1.6. Document Revision History for ASMI Parallel Intel® FPGA IP Core User Guide
1.2. Ports and Parameters x
1.2.1. Parameters 1.2.2. Input Ports 1.2.3. Output Ports
1.4. ASMI Parallel Intel® FPGA IP Core Operations and Timing Requirements x
1.4.1. Read Memory Capacity ID from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.2. Read Silicon ID from the EPCS Device 1.4.3. Protect a Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.4. Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.7. Read Status Register of the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.8. Erase Memory in a Specified Sector on the EPCS/EPCQ/EPCQ-L/EPCQ-A Device 1.4.9. Erase Memory in Bulk on the EPCS/EPCQ/EPCQ-L256/EPCQ-A Device 1.4.10. Erase Memory in a Specified Die on the EPCQ-L512 and EPCQ-L1024 Device 1.4.11. Enable 4-byte Addressing Operation for an EPCQ256/EPCQ-L256 or Larger Devices 1.4.12. 4-byte Addressing Exit Operation for an EPCQ256/EPCQ-L256 or Larger Devices
1.4.5. Fast Read Data from the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction 1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction
1.4.6. Write Data to the EPCS/EPCQ/EPCQ-L/EPCQ-A Device x
1.4.6.1. Single-Byte Write Operation 1.4.6.2. Page-Write Operation
1. ASMI Parallel Intel® FPGA IP Core User Guide

1.4.5.2. EPCQ/EPCQ-L/EPCQ-A Devices Read Dummy Clock Instruction

By default, the ASMI Parallel Intel® FPGA IP core disables the Read device dummy clock option and uses the default dummy clock value in the Quad-Serial Configuration (EPCQ) Devices Datasheet, EPCQ-L Serial Configuration Devices Datasheet, or EPCQ-A Serial Configuration Device Datasheet.

Although you can configure the dummy clock value in the EPCQ/EPCQ-L/EPCQ-A device, the dummy clock value must be in accordance to the value in the Quad-Serial Configuration (EPCQ) Devices Datasheet, EPCQ-L Serial Configuration Devices Datasheet, or EPCQ-A Serial Configuration Device Datasheet. If you configure the dummy clock value in the EPCQ/EPCQ-L/EPCQ-A device other than default value, the fast read operation fails.

To perform the fast read operation without changing the dummy clock value in the EPCQ/EPCQ-L/EPCQ-A device, enable the Read device dummy clock option. The ASMI Parallel Intel® FPGA IP core configures the dummy clock value to match with the EPCQ/EPCQ-L/EPCQ-A device. When enabling the Read device dummy clock option, the ASMI Parallel Intel® FPGA IP core reads the nonvolatile configuration register of the EPCQ/EPCQ-L/EPCQ-A device for the dummy clock value at the beginning of clock cycles. This dummy clock value is held until the read_dummyclk signal is asserted or until the device resets.

To read the dummy clock value from the volatile configuration register of the EPCQ/EPCQ-L/EPCQ-A device, assert at least one clock cycle of the read_dummyclk signal. The ASMI Parallel Intel® FPGA IP core asserts the busy signal after receiving the read_dummyclk signal. The busy signal remains asserted to indicate operation is in progress and deasserted whenever the operation is completed. If the read_dummyclk signal remains asserted while the busy signal is deasserted after the IP core finishes the operation, the IP core re-registers the operation and carries out the operation again. So, the read_dummyclk signal must be deasserted before the busy signal is deasserted. The dummy clock value is held until the next read_dummyclk signal is asserted or until the device resets.

Figure 11. Read Dummy Clock InstructionThis figure does not reflect the true processing time.
Note: When the busy signal is deasserted, allow two clock cycles before sending a new signal. This delay allows the circuit to reset itself before executing the next command.


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