Visible to Intel only — GUID: sam1412044626569
Ixiasoft
Visible to Intel only — GUID: sam1412044626569
Ixiasoft
1.4.5.1. EPCQ/EPCQ-L/EPCQ-A Devices Extended SPI Dual and Quad I/O Instruction
For EPCS/EPCQ/EPCQ-L/EPCQ-A devices, the IP core generates the first data byte on the dataout[7..0] port after eight cycles and then it appears for the read command. The eight cycles are the dummy clock cycles designated in ASMI Parallel Intel® FPGA IP core in accordance to the default dummy clock value in the EPCS/EPCQ/EPCQ-L/EPCQ-A datasheet. The EPCS/EPCQ/EPCQ-L/EPCQ-A standard I/O and EPCQ/EPCQ-L/EPCQ-A dual I/O have default dummy clock value of 8, while EPCQ/EPCQ-L/EPCQ-A quad I/O has default dummy clock value of 10. So, when selecting EPCQ/EPCQ-L/EPCQ-A quad I/O fast read operation, the IP core generates the first byte of data on the dataout[7..0]port after ten cycles, and then it appears for the read command.
If the rden signal is asserted for the subsequence data, the data from the next address appears on the dataout[7..0] port at every eight clock cycles for standard I/O, every four clock cycles for dual I/O, and every two clock cycles for quad I/O. Monitor the data_valid signal to ensure that you sample the dataout[7..0] signal only when the data_valid signal is asserted.
When you enable multiple I/O in fast read operation, the fast read and write operations have their equivalents in multiple I/O. Instruction operation codes are sent in DQ0 and the rest of data will be transferred in multiple data lines. Other instructions such as sector erase, read status, and others still operates in standard I/O mode.