Visible to Intel only — GUID: nik1411172650017
Ixiasoft
Visible to Intel only — GUID: nik1411172650017
Ixiasoft
3.3.1. LL 100GbE IP Core Signals
The signals of the LL 100GbE IP core are described in the following formats:
- The figure identifies the IP core interfaces.
- Tables list the signals and the interfaces to which they belong.
- Links guide you to descriptions for the individual signals, by interface. The links appear in Related Links.
Signal Name |
Direction |
Interface |
---|---|---|
clk_ref | Input |
Clocks |
clk_rx_recover | Output | Clocks This signal is only available if you turn on Enable SyncE in the parameter editor. |
reset_async | Input |
Reset |
tx_serial[9:0] tx_serial[3:0] (CAUI–4) |
Output |
Transceiver PHY serial data interface |
rx_pcs_ready | Output |
PHY status |
tx_lanes_stable | Output | |
clk_txmac_in | Input | Clocks Interface to external TX MAC PLL This signal is only available if you turn on Enable external TX MAC PLL in the parameter editor. |
clk_txmac | Output |
Clocks TX client interface |
l8_tx_data[511:0] |
Input |
Avalon-ST TX client interface Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces. |
l8_tx_empty[5:0] |
Input |
|
l8_tx_startofpacket |
Input |
|
l8_tx_endofpacket |
Input |
|
l8_tx_ready |
Output |
|
l8_tx_valid |
Input |
|
l8_tx_error |
Input | |
din[255:0] |
Input |
Custom streaming TX client interface Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces. |
din_sop[3:0] |
Input |
|
din_eop[3:0] |
Input |
|
din_eop_empty[11:0] |
Input |
|
din_idle[3:0] |
Input |
|
din_req |
Output |
|
tx_error[3:0] |
Input | |
clk_rxmac | Output |
Clocks RX client interface |
l8_rx_data[511:0] |
Output |
Avalon-ST RX client interface Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces. |
l8_rx_empty[5:0] |
Output |
|
l8_rx_startofpacket |
Output |
|
l8_rx_endofpacket |
Output |
|
l8_rx_error[5:0] |
Output |
|
l8_rx_valid |
Output |
|
l8_rx_fcs_valid |
Output |
|
l8_rx_fcs_error |
Output |
|
l8_rx_status[2:0] |
Output | |
dout_d[255:0] |
Output |
Custom streaming RX client interface Each IP core instance has Avalon-ST TX and RX client interfaces, or custom streaming TX and RX client interfaces. |
dout_c[31:0] |
Output |
|
dout_sop[3:0] |
Output |
|
dout_eop[3:0] |
Output |
|
dout_eop_empty[11:0] |
Output | |
dout_idle[3:0] |
Output | |
rx_error[5:0] | Output | |
rx_fcs_error | Output |
|
rx_fcs_valid | Output |
|
rx_status[2:0] | Output | |
dout_valid | Output |
|
pause_insert_tx[<N>-1:0] | Input |
Pause control and generation interface |
pause_receive_rx[<N>-1:0] | Output |
|
remote_fault_status | Output |
Link fault signaling interface These signals are available only in IP core variations that include the link fault signaling module. |
local_fault_status | Output |
|
unidirectional_en | Output | Link fault signaling interface, Clause 66 status These signals are available only in IP core variations that include the link fault signaling module. |
link_fault_gen_en | Output | |
tx_inc_64 | Output |
TX statistics counter increment vectors These signals are available whether or not your IP core includes TX statistics counters. |
tx_inc_127 | Output |
|
tx_inc_255 | Output |
|
tx_inc_511 | Output |
|
tx_inc_1023 | Output |
|
tx_inc_1518 | Output |
|
tx_inc_max | Output |
|
tx_inc_over | Output |
|
tx_inc_mcast_data_err | Output |
|
tx_inc_mcast_data_ok | Output |
|
tx_inc_bcast_data_err | Output |
|
tx_inc_bcast_data_ok | Output |
|
tx_inc_ucast_data_err | Output |
|
tx_inc_ucast_data_ok | Output |
|
tx_inc_mcast_ctrl | Output |
|
tx_inc_bcast_ctrl | Output |
|
tx_inc_ucast_ctrl | Output |
|
tx_inc_pause | Output |
|
tx_inc_fcs_err | Output |
|
tx_inc_fragment | Output |
|
tx_inc_jabber | Output |
|
tx_inc_sizeok_fcserr | Output |
|
rx_inc_runt | Output |
RX statistics counter increment vectors These signals are available whether or not your IP core includes RX statistics counters. |
rx_inc_64 | Output |
|
rx_inc_127 | Output |
|
rx_inc_255 | Output |
|
rx_inc_511 | Output |
|
rx_inc_1023 | Output |
|
rx_inc_1518 | Output |
|
rx_inc_max | Output |
|
rx_inc_over | Output |
|
rx_inc_mcast_data_err | Output |
|
rx_inc_mcast_data_ok | Output |
|
rx_inc_bcast_data_err | Output |
|
rx_inc_bcast_data_ok | Output |
|
rx_inc_ucast_data_err | Output |
|
rx_inc_ucast_data_ok | Output |
|
rx_inc_mcast_ctrl | Output |
|
rx_inc_bcast_ctrl | Output |
|
rx_inc_ucast_ctrl | Output |
|
rx_inc_pause | Output |
|
rx_inc_fcs_err | Output |
|
rx_inc_fragment | Output |
|
rx_inc_jabber | Output |
|
rx_inc_sizeok_fcserr | Output |
|
rx_inc_pause_ctrl_err | Output |
|
rx_inc_mcast_ctrl_err | Output |
|
rx_inc_bcast_ctrl_err | Output |
|
rx_inc_ucast_ctrl_err | Output |
|
tx_inc_octetsOK[15:0] | Output | OctetOK Count interface |
tx_inc_octetsOK_valid | Output | |
rx_inc_octetsOK[15:0] | Output | |
rx_inc_octetsOK_valid | Output | |
clk_status | Input |
Clocks Control and status interface |
reset_status | Input |
Resets Control and status interface |
status_addr[15:0] | Input |
Control and status interface |
status_read | Input |
|
status_write | Input |
|
status_writedata[31:0] | Input |
|
status_readdata[31:0] | Output |
|
status_readdata_valid | Output |
|
status_waitrequest |
Output |
|
status_read_timeout | Output |
|
tx_time_of_day_96b_data[95:0] | Input | 1588 PTP interface These signals are available only if 1588 PTP functionality is included in the IP core. |
tx_time_of_day_64b_data[63:0] | Input | |
rx_time_of_day_96b_data[95:0] | Input | |
rx_time_of_day_64b_data[63:0] | Input | |
tx_etstamp_ins_ctrl_timestamp_insert | Input | |
tx_etstamp_ins_ctrl_residence_time_update | Input | |
tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] | Input |
|
tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] | Input |
|
tx_etstamp_ins_ctrl_timestamp_format | Input |
|
tx_etstamp_ins_ctrl_residence_time_calc_format | Input |
|
tx_etstamp_ins_ctrl_offset_timestamp[15:0] | Input |
|
tx_etstamp_ins_ctrl_offset_correction_field[15:0] | Input |
|
tx_etstamp_ins_ctrl_checksum_zero | Input |
|
tx_etstamp_ins_ctrl_offset_checksum_field[15:0] | Input |
|
tx_etstamp_ins_ctrl_checksum_correct | Input |
|
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0] | Input |
|
tx_egress_asymmetry_update | Input |
|
tx_egress_timestamp_request_valid | Input |
|
tx_egress_timestamp_96b_data[95:0] | Output |
|
tx_egress_timestamp_96b_valid | Output |
|
tx_egress_timestamp_64b_data[63:0] | Output |
|
tx_egress_timestamp_64b_valid | Output |
|
tx_egress_timestamp_request_fingerprint[(W–1):0] | Input |
|
tx_egress_timestamp_96b_fingerprint[(W–1):0] | Output |
|
tx_egress_timestamp_64b_fingerprint[(W–1):0] | Output |
|
rx_ingress_timestamp_96b_data[95:0] | Output |
|
rx_ingress_timestamp_96b_valid | Output | |
rx_ingress_timestamp_64b_data[63:0] | Output |
|
rx_ingress_timestamp_64b_valid | Output |
|
reconfig_to_xcvr[1399:0] |
Input |
Interface to Stratix V reconfiguration controller These signals are available in Stratix V devices only. |
reconfig_from_xcvr[919:0] |
Output |
|
reconfig_busy | Input |
|
reconfig_clk | Input |
Clocks Arria 10 Native PHY IP core reconfiguration interface This signal is available in Arria 10 devices only. |
reconfig_reset | Input |
Resets Arria 10 Native PHY IP core reconfiguration interface This signal is available in Arria 10 devices only. |
reconfig_address [13:0] reconfig_address [11:0] (CAUI-4) |
Input |
Arria 10 Native PHY IP core reconfiguration interface These signals are available in Arria 10 devices only. |
reconfig_read | Input |
|
reconfig_write | Input |
|
reconfig_writedata[31:0] | Input |
|
reconfig_readdata[31:0] | Output |
|
reconfig_waitrequest | Output |
|
pll_locked | Input |
External transceiver PLL interface. These signals are available in Arria 10 devices only. |
tx_serial_clk[9:0] tx_serial_clk[3:0] (CAUI–4) |
Input |