Visible to Intel only — GUID: bdm1478126680343
Ixiasoft
Visible to Intel only — GUID: bdm1478126680343
Ixiasoft
2.8.2.6. Testbench Output Example
This section shows successful simulation using the LL 100GbE IP core testbench (<variation_name> _example_design/alt_eth_ultra/example_testbench/basic_avl_tb_top.v for Stratix V variations, or <example_design_directory> /example_testbench/basic_avl_tb_top.v for Arria 10 variations). The testbench connects the Ethernet TX lanes to the Ethernet RX lanes, so that the IP core is in an external loopback configuration. In simulation, the testbench resets the IP core and waits for lane alignment and deskew to complete successfully. The packet generator sends ten packets on the Ethernet TX lanes and the packet checker checks the packets when the IP core receives them on the Ethernet RX lanes.
The successful testbench run displays the following output:
# *****************************************
# ** Starting TX traffic...
# **
# **
# ** Sending Packet 1...
# ** Sending Packet 2...
# ** Sending Packet 3...
# ** Sending Packet 4...
# ** Sending Packet 5...
# ** Sending Packet 6...
# ** Sending Packet 7...
# ** Sending Packet 8...
# ** Sending Packet 9...
# ** Sending Packet 10...
# ** Received Packet 1...
# ** Received Packet 2...
# ** Received Packet 3...
# ** Received Packet 4...
# ** Received Packet 5...
# ** Received Packet 6...
# ** Received Packet 7...
# ** Received Packet 8...
# ** Received Packet 9...
# ** Received Packet 10...
# **
# ** Testbench complete.
# **
# *****************************************