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2.1. Installation and Licensing for LL 100GbE IP Core for Stratix® V Devices
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. IP Core Testbenches
2.9. Compiling the Full Design and Programming the FPGA
2.10. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices
2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.6. External TX MAC PLL
2.7.7. Placement Settings for the LL 100GbE Core
3.2.1. LL 100GbE IP Core TX Datapath
3.2.2. LL 100GbE IP Core TX Data Bus Interfaces
3.2.3. LL 100GbE IP Core RX Datapath
3.2.4. LL 100GbE IP Core RX Data Bus Interfaces
3.2.5. Low Latency 100GbE CAUI–4 PHY
3.2.6. External Reconfiguration Controller
3.2.7. External Transceiver PLL
3.2.8. External TX MAC PLL
3.2.9. Congestion and Flow Control Using Pause Frames
3.2.10. Pause Control and Generation Interface
3.2.11. Pause Control Frame Filtering
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. 1588 Precision Time Protocol Interfaces
3.2.15. PHY Status Interface
3.2.16. Transceiver PHY Serial Data Interface
3.2.17. Control and Status Interface
3.2.18. Arria 10 Transceiver Reconfiguration Interface
3.2.19. Clocks
3.2.20. Resets
3.2.2.1. LL 100GbE IP Core User Interface Data Bus
3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. LL 100GbE IP Core RX Filtering
3.2.3.2. LL 100GbE IP Core Preamble Processing
3.2.3.3. LL 100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. LL 100GbE IP Core CRC Checking
3.2.3.5. LL 100GbE IP Core Malformed Packet Handling
3.2.3.6. RX CRC Forwarding
3.2.3.7. Inter-Packet Gap
3.2.3.8. RX RSFEC
3.2.3.9. Pause Ignore
3.2.3.10. Control Frame Identification
3.4.1.1. PHY Registers
3.4.1.2. Link Fault Signaling Registers
3.4.1.3. LL 100GbE IP Core MAC Configuration Registers
3.4.1.4. Pause Registers
3.4.1.5. TX Statistics Registers
3.4.1.6. RX Statistics Registers
3.4.1.7. 1588 PTP Registers
3.4.1.8. TX Reed-Solomon FEC Registers
3.4.1.9. RX Reed-Solomon FEC Registers
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2.3. Specifying the IP Core Parameters and Options
The LL 100GbE parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus Prime software.
- In the IP Catalog (Tools > IP Catalog), select a target device family. The LL 100GbE IP core is not supported in Platform Designer (Standard).
- In the IP Catalog, locate and double-click the name of the IP core to customize (Low Latency 100G Ethernet ). The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file with one of the following names:
- <your_ip> .qsys (for Arria 10 variations generated in the Intel® Quartus® Prime Standard Edition software)
- <your_ip> .ip (for Arria 10 variations generated in the Intel® Quartus® Prime Pro Edition software)
- <your_ip> .qip (for Stratix V variations)
- If your IP core targets the Arria 10 device family, you must select a specific device in the Device field or maintain the default device the Quartus Prime software lists. If you target a specific Intel development kit, the hardware design example overwrites the selection with the device on the target board.
- Click OK. The parameter editor appears.
- Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following. Refer to your IP core user guide for information about specific IP core parameters.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
- A functional VHDL IP core is not available. Specify Verilog HDL only, for your IP core variation.
- For Arria 10 variations, follow these steps:
- Optionally, to generate a simulation testbench or example project, follow the instructions in Generating the LL 100GbE Testbench.
- Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
- Click Finish. The parameter editor adds the top-level .qsys file to the current project automatically. If you are prompted to manually add the .qsys or .ip file to the project, click Project > Add/Remove Files in Project to add the file.
- For Stratix V variations, follow these steps:
- Click Finish.
- Optionally, to generate a simulation testbench or example project, follow the instructions in Generating the LL 100GbE Testbench.
After you click Finish and optionally follow the additional step to generate a simulation testbench and example project, if available for your IP core variation, the parameter editor adds the top-level .qip file to the current project automatically. If you are prompted to manually add this file to the project, click Project > Add/Remove Files in Project to add the file.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.