Visible to Intel only — GUID: wpe1478724497489
Ixiasoft
Visible to Intel only — GUID: wpe1478724497489
Ixiasoft
3.2.17. Control and Status Interface
The control and status interface provides an Avalon-MM interface to the IP core control and status registers. The Avalon-MM interface implements a standard memory-mapped protocol. You can connect an embedded processor or JTAG Avalon master to this bus to access the control and status registers.
This interface cannot handle multiple pending read transfers. Despite the presence of the status_readdata_valid signal, this Avalon-MM interface is non-pipelined with variable latency.
Signal Name |
Direction |
Description |
---|---|---|
status_addr [15:0] |
Input |
Address for reads and writes |
status_read |
Input |
Read command |
status_write |
Input |
Write command |
status_writedata [31:0] |
Input |
Data to be written |
status_readdata [31:0] |
Output |
Read data |
status_readdata_valid |
Output |
Read data is ready for use |
status_waitrequest |
Output |
Busy signal indicating control and status interface cannot currently respond to requests |
status_read_timeout |
Output |
Timeout signal indicating read data did not arrive when expected. Hardwired timeout counter is set so that this timeout should only occur in the presence of an error condition, such as status_addr with an undefined value. This signal is not an Avalon-MM defined signal |
The status interface is designed to operate at a low frequencies, typically 100 MHz, so that control and status logic does not compete for resources with the surrounding high speed datapath.