Low Latency 100-Gbps Ethernet IP Core User Guide

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ID 683160
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the LL 100GbE IP Core 2. Getting Started 3. Functional Description 4. Debugging the Link A. Additional Information
1. About the LL 100GbE IP Core x
1.1. LL 100GbE IP Core Supported Features 1.2. IP Core Device Family and Speed Grade Support 1.3. IP Core Verification 1.4. Performance and Resource Utilization 1.5. Release Information
1.2. IP Core Device Family and Speed Grade Support x
1.2.1. LL 100GbE IP Core Device Family Support 1.2.2. LL 100GbE IP Core Device Speed Grade Support
1.3. IP Core Verification x
1.3.1. Simulation Environment 1.3.2. Compilation Checking 1.3.3. Hardware Testing
1.4. Performance and Resource Utilization x
1.4.1. Arria 10 Resource Utilization 1.4.2. Stratix V Resource Utilization
2. Getting Started x
2.1. Installation and Licensing for LL 100GbE IP Core for Stratix® V Devices 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options 2.4. IP Core Parameters 2.5. Files Generated for Stratix V Variations 2.6. Files Generated for Arria 10 Variations 2.7. Integrating Your IP Core in Your Design 2.8. IP Core Testbenches 2.9. Compiling the Full Design and Programming the FPGA 2.10. Initializing the IP Core
2.2. Installing and Licensing Intel® FPGA IP Cores x
2.2.1. Intel® FPGA IP Evaluation Mode
2.7. Integrating Your IP Core in Your Design x
2.7.1. Pin Assignments 2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs 2.7.3. Transceiver PLL Required in Arria 10 Designs 2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices 2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.6. External TX MAC PLL 2.7.7. Placement Settings for the LL 100GbE Core
2.8. IP Core Testbenches x
2.8.1. Testbench Behavior 2.8.2. Simulating the LL 100GbE IP Core With the Testbenches
2.8.2. Simulating the LL 100GbE IP Core With the Testbenches x
2.8.2.1. Generating the LL 100GbE Testbench 2.8.2.2. Optimizing the IP Core Simulation With the Testbenches 2.8.2.3. Simulating with the Modelsim Simulator 2.8.2.4. Simulating with the NCSim Simulator 2.8.2.5. Simulating with the VCS Simulator 2.8.2.6. Testbench Output Example
3. Functional Description x
3.1. High Level System Overview 3.2. LL 100GbE IP Core Functional Description 3.3. Signals 3.4. Software Interface: Registers 3.5. Ethernet Glossary
3.2. LL 100GbE IP Core Functional Description x
3.2.1. LL 100GbE IP Core TX Datapath 3.2.2. LL 100GbE IP Core TX Data Bus Interfaces 3.2.3. LL 100GbE IP Core RX Datapath 3.2.4. LL 100GbE IP Core RX Data Bus Interfaces 3.2.5. Low Latency 100GbE CAUI–4 PHY 3.2.6. External Reconfiguration Controller 3.2.7. External Transceiver PLL 3.2.8. External TX MAC PLL 3.2.9. Congestion and Flow Control Using Pause Frames 3.2.10. Pause Control and Generation Interface 3.2.11. Pause Control Frame Filtering 3.2.12. Link Fault Signaling Interface 3.2.13. Statistics Counters Interface 3.2.14. 1588 Precision Time Protocol Interfaces 3.2.15. PHY Status Interface 3.2.16. Transceiver PHY Serial Data Interface 3.2.17. Control and Status Interface 3.2.18. Arria 10 Transceiver Reconfiguration Interface 3.2.19. Clocks 3.2.20. Resets
3.2.1. LL 100GbE IP Core TX Datapath x
3.2.1.1. Preamble, Start, and SFD Insertion 3.2.1.2. Address Insertion 3.2.1.3. Length/Type Field Processing 3.2.1.4. Frame Padding 3.2.1.5. Frame Check Sequence (CRC-32) Insertion 3.2.1.6. Inter-Packet Gap Generation and Insertion 3.2.1.7. TX RSFEC 3.2.1.8. Error Insertion Test and Debug Feature
3.2.2. LL 100GbE IP Core TX Data Bus Interfaces x
3.2.2.1. LL 100GbE IP Core User Interface Data Bus 3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface) 3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface) 3.2.2.4. Bus Quantization Effects With Adapters 3.2.2.5. User Interface to Ethernet Transmission
3.2.2.5. User Interface to Ethernet Transmission x
3.2.2.5.1. Order of Transmission
3.2.3. LL 100GbE IP Core RX Datapath x
3.2.3.1. LL 100GbE IP Core RX Filtering 3.2.3.2. LL 100GbE IP Core Preamble Processing 3.2.3.3. LL 100GbE IP Core FCS (CRC-32) Removal 3.2.3.4. LL 100GbE IP Core CRC Checking 3.2.3.5. LL 100GbE IP Core Malformed Packet Handling 3.2.3.6. RX CRC Forwarding 3.2.3.7. Inter-Packet Gap 3.2.3.8. RX RSFEC 3.2.3.9. Pause Ignore 3.2.3.10. Control Frame Identification
3.2.4. LL 100GbE IP Core RX Data Bus Interfaces x
3.2.4.1. LL 100GbE IP Core User Interface Data Bus 3.2.4.2. LL 100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface) 3.2.4.3. LL 100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
3.2.9. Congestion and Flow Control Using Pause Frames x
3.2.9.1. Conditions Triggering XOFF Frame Transmission 3.2.9.2. Conditions Triggering XON Frame Transmission
3.2.13. Statistics Counters Interface x
3.2.13.1. OctetOK Count Interface
3.2.14. 1588 Precision Time Protocol Interfaces x
3.2.14.1. Implementing a 1588 System That Includes a LL 100GbE Core 3.2.14.2. PTP Receive Functionality 3.2.14.3. PTP Transmit Functionality 3.2.14.4. External Time-of-Day Module for 1588 PTP Variations 3.2.14.5. PTP Timestamp and TOD Formats 3.2.14.6. 1588 PTP Interface Signals
3.3. Signals x
3.3.1. LL 100GbE IP Core Signals
3.4. Software Interface: Registers x
3.4.1. LL 100GbE IP Core Registers 3.4.2. LL 100GbE Hardware Design Example Registers
3.4.1. LL 100GbE IP Core Registers x
3.4.1.1. PHY Registers 3.4.1.2. Link Fault Signaling Registers 3.4.1.3. LL 100GbE IP Core MAC Configuration Registers 3.4.1.4. Pause Registers 3.4.1.5. TX Statistics Registers 3.4.1.6. RX Statistics Registers 3.4.1.7. 1588 PTP Registers 3.4.1.8. TX Reed-Solomon FEC Registers 3.4.1.9. RX Reed-Solomon FEC Registers
3.4.2. LL 100GbE Hardware Design Example Registers x
3.4.2.1. Packet Client Registers
4. Debugging the Link x
4.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy
A. Additional Information x
A.1. LL 100GbE IP Core User Guide Archives A.2. LL 100GbE IP Core User Guide Revision History
1. About the LL 100GbE IP Core
2. Getting Started
3. Functional Description
4. Debugging the Link
A. Additional Information

3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)

The LL 100GbE IP core TX datapath with adapters employs the Avalon-ST protocol. The Avalon-ST protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:

  • Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
  • The SOP must always be in the MSB, simplifying the interpretation and processing of incoming data.
  • A valid signal qualifies signals from source to sink.
  • The sink applies backpressure to the source by using the ready signal. The source typically responds to the deassertion of the ready signal from the sink by driving the same data until the sink can accept it. The readyLatency defines the relationship between assertion and deassertion of the ready signal, and cycles which are considered to be ready for data transfer.The readyLatency on the TX client interface is zero cycles.

The client acts as a source and the TX MAC acts as a sink in the transmit direction.

Figure 11. TX Client to MAC Interface with Adapters (Avalon-ST)
Table 16.  Signals of the Avalon-ST TX Client InterfaceAll interface signals are clocked by the clk_txmac clock.

Signal Name

Direction

Description

l8_tx_data[511:0]

Input

TX data. If the preamble pass-through feature is enabled, data begins with the preamble.

The LL 100GbE IP core does not process incoming frames of less than nine bytes correctly. You must ensure such frames do not reach the TX client interface.

You must send each TX data packet without intermediate IDLE cycles. Therefore, you must ensure your application can provide the data for a single packet in consecutive clock cycles. If data might not be available otherwise, you must buffer the data in your design and wait to assert l8_tx_startofpacket when you are assured the packet data to send on l8_tx_data[511:0] is available or will be available on time.

l8_tx_empty[5:0]

Input

Indicates the number of empty bytes on l8_tx_data[511:0] when l8_tx_endofpacket is asserted.

l8_tx_startofpacket

Input

When asserted, indicates the start of a packet. The packet starts on the MSB.

l8_tx_endofpacket

Input

When asserted, indicates the end of packet.

l8_tx_ready

Output

When asserted, the MAC is ready to receive data. The l8_tx_ready signal acts as an acknowledge. The source drives l8_tx_valid and l8_tx_data[511:0], then waits for the sink to assert l8_tx_ready. The readyLatency is zero cycles, so that the IP core accepts valid data in the same cycle in which it asserts l8_tx_ready.

The l8_tx_ready signal indicates the MAC is ready to receive data in normal operational model. However, the l8_tx_ready signal might not be an adequate indication following reset. To avoid sending packets before the Ethernet link is able to transmit them reliably, you should ensure that the application does not send packets on the TX client interface until after the tx_lanes_stable signal is asserted.

l8_tx_valid

Input

When asserted l8_tx_data is valid. This signal must be continuously asserted between the assertions of l8_tx_startofpacket and l8_tx_endofpacket for the same packet.

l8_tx_error

Input When asserted in an EOP cycle (while l8_tx_endofpacket is asserted), directs the IP core to insert an error in the packet before sending it on the Ethernet link.

This signal is a test and debug feature. In loopback mode, the IP core recognizes the packet upon return as a malformed packet.

Figure 12. Traffic on the TX and RX Avalon-ST Client Interface for Low Latency 100GbE IP CoreShows typical traffic for the TX and RX Avalon-ST interface of the 100GbE IP core.
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