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2.1. Installation and Licensing for LL 100GbE IP Core for Stratix® V Devices
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options
2.4. IP Core Parameters
2.5. Files Generated for Stratix V Variations
2.6. Files Generated for Arria 10 Variations
2.7. Integrating Your IP Core in Your Design
2.8. IP Core Testbenches
2.9. Compiling the Full Design and Programming the FPGA
2.10. Initializing the IP Core
2.7.1. Pin Assignments
2.7.2. External Transceiver Reconfiguration Controller Required in Stratix V Designs
2.7.3. Transceiver PLL Required in Arria 10 Designs
2.7.4. Handling Potential Jitter in Intel® Arria® 10 Devices
2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature
2.7.6. External TX MAC PLL
2.7.7. Placement Settings for the LL 100GbE Core
3.2.1. LL 100GbE IP Core TX Datapath
3.2.2. LL 100GbE IP Core TX Data Bus Interfaces
3.2.3. LL 100GbE IP Core RX Datapath
3.2.4. LL 100GbE IP Core RX Data Bus Interfaces
3.2.5. Low Latency 100GbE CAUI–4 PHY
3.2.6. External Reconfiguration Controller
3.2.7. External Transceiver PLL
3.2.8. External TX MAC PLL
3.2.9. Congestion and Flow Control Using Pause Frames
3.2.10. Pause Control and Generation Interface
3.2.11. Pause Control Frame Filtering
3.2.12. Link Fault Signaling Interface
3.2.13. Statistics Counters Interface
3.2.14. 1588 Precision Time Protocol Interfaces
3.2.15. PHY Status Interface
3.2.16. Transceiver PHY Serial Data Interface
3.2.17. Control and Status Interface
3.2.18. Arria 10 Transceiver Reconfiguration Interface
3.2.19. Clocks
3.2.20. Resets
3.2.2.1. LL 100GbE IP Core User Interface Data Bus
3.2.2.2. LL 100GbE IP Core TX Data Bus with Adapters (Avalon-ST Interface)
3.2.2.3. LL 100GbE IP Core TX Data Bus Without Adapters (Custom Streaming Interface)
3.2.2.4. Bus Quantization Effects With Adapters
3.2.2.5. User Interface to Ethernet Transmission
3.2.3.1. LL 100GbE IP Core RX Filtering
3.2.3.2. LL 100GbE IP Core Preamble Processing
3.2.3.3. LL 100GbE IP Core FCS (CRC-32) Removal
3.2.3.4. LL 100GbE IP Core CRC Checking
3.2.3.5. LL 100GbE IP Core Malformed Packet Handling
3.2.3.6. RX CRC Forwarding
3.2.3.7. Inter-Packet Gap
3.2.3.8. RX RSFEC
3.2.3.9. Pause Ignore
3.2.3.10. Control Frame Identification
3.4.1.1. PHY Registers
3.4.1.2. Link Fault Signaling Registers
3.4.1.3. LL 100GbE IP Core MAC Configuration Registers
3.4.1.4. Pause Registers
3.4.1.5. TX Statistics Registers
3.4.1.6. RX Statistics Registers
3.4.1.7. 1588 PTP Registers
3.4.1.8. TX Reed-Solomon FEC Registers
3.4.1.9. RX Reed-Solomon FEC Registers
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1.1. LL 100GbE IP Core Supported Features
All LL 100GbE IP core variations include both a MAC and a PHY, and all variations are in full-duplex mode. These IP core variations offer the following features:
- Designed to the IEEE 802.3ba-2010 High Speed Ethernet Standard available on the IEEE website (www.ieee.org).
- Soft PCS logic that interfaces seamlessly to Intel FPGA 10.3125 Gbps and 25.78125 Gbps serial transceivers.
- Standard CAUI external interface consisting of ten FPGA hard serial transceiver lanes operating at 10.3125 Gbps , or the CAUI-4 external interface consisting of four FPGA hard serial transceiver lanes operating at 25.78125 Gbps.
- Supports Synchronous Ethernet (SyncE) by providing an optional CDR recovered clock output signal to the device fabric.
- Avalon® memory mapped (Avalon-MM) management interface to access the IP core control and status registers.
- Avalon® streaming (Avalon-ST) data path interface connects to client logic with the start of frame in the most significant byte (MSB) when optional adapters are used. Interface has data width 512 bits.
- Optional custom streaming data path interface with narrower bus width and a start frame possible on 64‑bit word boundaries without the optional adapters. Interface has data width 256 bits.
- Support for jumbo packets.
- TX and RX CRC pass-through control.
- Optional TX CRC generation and insertion.
- RX CRC checking and error reporting.
- TX error insertion capability supports test and debug.
- RX and TX preamble pass-through options for applications that require proprietary user management information transfer.
- TX automatic frame padding to meet the 64-byte minimum Ethernet frame length at the LL 100GbE Ethernet connection.
- RX malformed packet checking per IEEE specification.
- Hardware and software reset control.
- Pause frame filtering control.
- Received control frame type indication.
- MAC provides cut-through frame processing.
- Optional deficit idle counter (DIC) options to maintain a finely controlled 8-byte or 12-byte inter-packet gap (IPG) minimum average.
- Optional IEEE 802.3 Clause 31 Ethernet flow control operation using the pause registers or pause interface.
- Optional priority-based flow control that complies with the IEEE Standard 802.1Qbb-2011—Amendment 17: Priority-based Flow Control, using the pause registers for fine control.
- 1000 bits RX PCS lane skew tolerance, which exceeds the IEEE 802.3-2012 Ethernet standard clause 82.2.12 requirements.
- Optional support for the IEEE Standard 1588-2008 Precision Clock Synchronization Protocol (1588 PTP).
- Optional statistics counters.
- Optional fault signaling: detects and reports local fault and generates remote fault, with IEEE 802.3ba-2012 Ethernet Standard Clause 66 support.
- Optional serial PMA loopback (TX to RX) at the serial transceiver for self-diagnostic testing.
- Optional access to Native PHY Debug Master Endpoint (NPDME) for debugging or monitoring PHY signal integrity.
The LL 100GbE IP core can support full wire line speed with a 64-byte frame length and back-to-back or mixed length traffic with no dropped packets.
For a detailed specification of the Ethernet protocol refer to the IEEE 802.3ba-2010 High Speed Ethernet Standard.
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