Visible to Intel only — GUID: mbr1478667706684
Ixiasoft
Visible to Intel only — GUID: mbr1478667706684
Ixiasoft
3.2.4.3. LL 100GbE IP Core RX Data Bus Without Adapters (Custom Streaming Interface)
Signal Name |
Direction |
Description |
---|---|---|
dout_d[255:0] | Output |
Received data and Idle bytes. In RX preamble pass-through mode, this bus also carries the preamble. |
dout_c[31:0] | Output |
Indicates control bytes on the data bus. Each bit of dout_c indicates whether the corresponding byte of dout_d is a control byte. A bit is asserted high if the corresponding byte on dout_d is an Idle byte or the Start byte, and has the value of zero if the corresponding byte is a data byte or, in preamble pass-through mode, a preamble or SFD byte. |
dout_sop[3:0] | Output |
Indicates the first data word of a frame, in the current clk_rxmac cycle. In RX preamble pass-through mode, the first data word is the word that contains the preamble. When the RX preamble pass-through feature is turned off, the first data word is the first word of Ethernet data that follows the preamble. This signal is one-hot encoded. |
dout_eop[3:0] | Output |
Indicates the final word of a frame in the current clk_rxmac cycle. If CRC removal is disabled, this signal indicates the word with the final CRC byte. If CRC removal is enabled, this signal indicates the final word with data. This signal is one-hot encoded. In the case of an undersized packet, dout_sop and dout_eop might be non-zero in the same clock cycle. |
dout_eop_empty[11:0] | Output | Indicates the number of empty (invalid) bytes in the end-of-packet 8-byte word indicated by dout_eop. If dout_eop[z] has the value of 0, then the IP core sets the value of dout_eop_empty[(z+2):z] to 0. However, if dout_eop[z] has the value of 1, then you must use the value of dout_eop_empty[(z+2):z] to determine the number of empty (invalid) bytes in the end-of-packet word (and therefore, the end-of-packet byte). For example, if you have a LL 100GbE IP core and you observe that in the current clk_rxmac clock cycle, dout_eop has the value of 4'b0100 and dout_eop_empty has the value of 12'b000_110_000_000, you can conclude that byte 6 in word 2 of dout_d is an end-of-packet byte. |
dout_idle[3:0] | Output | Indicates the words in dout_d that hold Idle bytes or control information rather than Ethernet data. This signal is one-hot encoded. |
rx_error[5:0] | Output | Reports certain types of errors in the Ethernet frame whose contents are currently being transmitted on the client interface. This signal is valid in EOP cycles only. To ensure you can identify the corresponding packet, you must turn on Enable alignment EOP on FCS word in the LL 100GbE parameter editor. The individual bits report different types of errors:
|
rx_fcs_error | Output |
The current or most recent EOP byte is part of a frame with an incorrect FCS (CRC-32) value. By default, the IP core asserts rx_fcs_error in the same cycle as the dout_eop signal. However, if you turn off Enable alignment EOP on FCS word in the LL 100GbE parameter editor, the rx_fcs_error signal might lag the dout_eop signal for the frame. Runt frames always force an FCS error condition. However, if a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it as a runt. |
rx_fcs_valid | Output |
When set, indicates that rx_fcs_error has a valid value in the current clock cycle. |
rx_status[2:0] | Output | Indicates the IP core received a control frame on the Ethernet link. This signal identifies the type of control frame the IP core is passing through to the client interface. This signal is valid in EOP cycles only. To ensure you can identify the corresponding packet, you must turn on Enable alignment EOP on FCS word in the LL 100GbE parameter editor. The individual bits report different types of received control frames:
|
dout_valid | Output |
The dout_d bus contents are valid. This signal is occasionally deasserted due to clock crossing. |
clk_rxmac | Output |
RX MAC clock. The clock frequency should be 390.625 MHz. The clk_rxmac clock is derived from the recovered CDR clock. |
The data bytes use 100 Gigabit Media Independent Interface (CGMII-like) encoding. For packet payload bytes, the dout_c bit is set to 0 and the dout_d byte is the packet data. You can use this information to transmit out-of-spec data such as customized preambles when implementing non-standard variants of the IEEE 802.3ba-2010 High Speed Ethernet Standard.
In RX preamble pass-through mode, dout_c has the value of 1 while the start byte of the preamble is presented on the RX interface, and dout_c has the value of 0 while the remainder of the preamble sequence (six-byte preamble plus SFD byte) is presented on the RX interface.