Visible to Intel only — GUID: bmv1478667675363
Ixiasoft
Visible to Intel only — GUID: bmv1478667675363
Ixiasoft
3.2.4.2. LL 100GbE IP Core RX Data Bus with Adapters (Avalon-ST Interface)
The LL 100GbE IP core RX datapath employs the Avalon-ST protocol. The Avalon-ST protocol is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of data (sink). The key properties of this interface include:
- Start of packet (SOP) and end of packet (EOP) signals delimit frame transfers.
- The SOP must always be in the MSB, simplifying the interpretation and processing of data you receive on this interface.
- A valid signal qualifies signals from source to sink.
The RX MAC acts as a source and the client acts as a sink in the receive direction.
Name |
Direction |
Description |
---|---|---|
l8_rx_data[511:0] | Output |
RX data. |
l8_rx_empty[5:0] | Output |
Indicates the number of empty bytes on l8_rx_data[511:0] when l8_rx_endofpacket is asserted, starting from the least significant byte (LSB). |
l8_rx_startofpacket | Output |
When asserted, indicates the start of a packet. The packet starts on the MSB. |
l8_rx_endofpacket | Output |
When asserted, indicates the end of packet. In the case of an undersized packet, or in the case of a packet that is exactly 64 bytes long, l8_rx_startofpacket and l8_rx_endofpacket are asserted in the same clock cycle. |
l8_rx_error[5:0] | Output | Reports certain types of errors in the Ethernet frame whose contents are currently being transmitted on the client interface. This signal is valid in EOP cycles only. To ensure you can identify the corresponding packet, you must turn on Enable alignment EOP on FCS word in the LL 100GbE parameter editor. The individual bits report different types of errors:
|
l8_rx_valid | Output |
When asserted, indicates that RX data is valid. Only valid between the l8_rx_startofpacket and l8_rx_endofpacket signals. |
l8_rx_fcs_valid | Output |
When asserted, indicates that FCS is valid. |
l8_rx_fcs_error | Output |
When asserted, indicates an FCS error condition. The IP core asserts the l8_rx_fcs_error signal only when it asserts the l8_rx_fcs_valid signal. Runt frames always force an FCS error condition. However, if a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it as a runt. |
l8_rx_status[2:0] | Output | Indicates the IP core received a control frame on the Ethernet link. This signal identifies the type of control frame the IP core is passing through to the client interface. This signal is valid in EOP cycles only. To ensure you can identify the corresponding packet, you must turn on Enable alignment EOP on FCS word in the LL 100GbE parameter editor. The individual bits report different types of received control frames:
|