Visible to Intel only — GUID: ewo1416336571364
Ixiasoft
Visible to Intel only — GUID: ewo1416336571364
Ixiasoft
2.7.5. External Time-of-Day Module for Variations with 1588 PTP Feature
LL 100GbE IP cores that include the 1588 PTP module require an external time-of-day (TOD) module to provide a continuous flow of current time-of-day information. The TOD module must update the time-of-day output value on every clock cycle, and must provide the TOD value in the V2 format (96 bits) or the 64-bit TOD format, or both.
The example project you can generate for your IP core PTP variation includes a TOD module, implemented as two distinct, simple TOD modules, one connected to the TX MAC and one connected to the RX MAC.
TOD Module Signal | LL 100GbE IP Core Signal |
---|---|
rst_txmac (input) | Drive this signal from the same source as the reset_async input signal to the LL 100GbE IP core. |
rst_rxmac (input) | Drive this signal from the same source as the reset_async input signal to the LL 100GbE IP core. |
tod_txmclk_96b[95:0] (output) | tx_time_of_day_96b_data[95:0] (input) |
tod_txmclk_64b[63:0] (output) | tx_time_of_day_64b_data[63:0] (input) |
tod_rxmclk_96b[95:0] (output) | rx_time_of_day_96b_data[95:0] (input) |
tod_rxmclk_64b[63:0] (output) | rx_time_of_day_64b_data[63:0] (input) |
clk_txmac (input) | clk_txmac (output) |
clk_rxmac (input) | clk_rxmac (output) |