1.2.10. Power Supply Pins
Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Note: Altera recommends you to generate a .pin file from the Quartus® Prime Fitter to verify power pin assignment. Altera also recommends using this .pin file to determine if it is safe to power down or ground certain power supplies for your specific design. This step will inform you to make the appropriate design choices for unused power supplies for your design.
| Pin Name | Pin Functions | Pin Description | Connection Guidelines |
|---|---|---|---|
| VCCP | Power | VCCP supplies power to the periphery. | VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series . Use the Intel® FPGA Power and Thermal Calculator and the Quartus® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. |
| VCC | Power | VCC supplies power to the core. | VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator. For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series . Use the Intel® FPGA Power and Thermal Calculator and the Quartus® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board. |
| VCCPT | Power | Power supply for the IOPLL, programmable power technology, and I/O pre-drivers. | Connect VCCPT to a 1.8-V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:
Voltage spike ringing may be observed on VCCPT during device power-down sequencing if VCC is powered down before VCCPT, with the magnitude of the voltage spike ringing higher than VCCPT. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines . For the power rail sharing, refer to the Power Supply Sharing Guidelines for Agilex™ 7 Devices. |
| VCCRCORE | Power | CRAM power supply. For use in Agilex™ 7 production devices only (placed here for migration purposes). | Connect the VCCRCORE to 1.2-V power supply. You have the option to source VCCRCORE from the same regulator as VCCIO_PIO when VCCIO_PIO is connected to 1.2 V. |
| VCCH | Power | Analog Interface Bridge (AIB) and digital transceiver power supply. | Connect all VCCH pins to a 0.9-V low noise switching power supply for Agilex™ 7 devices with E-Tile and P-Tile. Connect all VCCH pins to a 0.8-V low noise switching power supply for Agilex™ 7 devices with F-Tile or R-Tile. For more details, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series . |
| VCCH_SDM | Power | Voltage rail sense. | Must connect this sense to the VCCH rail for the Agilex™ 7 devices with E-tile and P-tile. Must connect this sense to the VCC_HSSI_GXR if VCC_HSSI_GXR is powered to 0.9 V and connect this sense to VCCH if all VCC_HSSI_GXR pins are tied to GND when all R-Tiles are unused for the Agilex™ 7 devices with both F-Tile and R-Tile. Must connect this sense to the VCCH rail for the Agilex™ 7 device with F-Tile only. |
| VCCA_PLL | Power | I/O clock network power supply. | For Agilex™ 7 production devices and other Agilex™ 7 ES (except 2486A package) devices, connect VCCA_PLL to a 1.2-V low noise switching regulator. You have the option to source VCCA_PLL from the same regulator as VCCIO_PIO with proper isolation filtering. The VCCA_PLL rail must reside in Group 3 power rails. |
| VCCIO_PIO[2][A,B,C,D,E,F] VCCIO_PIO[3][A,B,C,D,E,F] |
Power | These are the supply voltage pins for the I/O banks. Each bank can support a different voltage level. Supported VCCIO standards include the following:
For more information about the supported pins, refer to the device pin-out file. |
Connect these pins to a 1.2-V or 1.5-V power supplies, depending on the I/O standard required by the specific bank. Connect the unused I/O bank power to 1.2V or 1.5V if the I/O bank will be used in future. Connect unused I/O bank power to GND and I/O pins floating if the I/O bank will not be used in future. Do not leave the VCCIO_PIO floating. If VCCIO_PIO_3A is tied to GND, connect VCCIO_PIO_SDM to VCCRCORE. During the power-up sequence only, a transient current whose magnitude is less than the VCCIO_PIO operating static current may be observed as the VCCIO_PIO transistors become operational. This is the expected behavior and will neither cause any functional failure nor reliability concerns to the device if the power-up or power-down sequence is followed. For more details, refer to the sensor monitoring system chapter in the Agilex™ 7 Power Management User Guide . For the power rail sharing, refer to the Power Supply Sharing Guidelines for Agilex™ 7 Devices. |
| VCCIO_PIO_SDM | Power | VCCIO_PIO voltage rail sense line. | Connect these pins to bank VCCIO_PIO_3A. You must supply 1.2 V to VCCIO_PIO_3A if you are using Avalon® streaming x16 or x32 mode. |
| VCCIO_SDM | Power | Configuration pins power supply. | Connect these pins to a 1.8-V power supply. For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines . For the power rail sharing, refer to the Power Supply Sharing Guidelines for Agilex™ 7 Devices. |
| VCCPLLDIG_SDM | Power | SDM block PLL power pins. | VCCPLLDIG_SDM must be sourced from the same regulator as VCCL_SDM with proper isolation filtering. |
| VCCL_SDM | Power | SDM power supply. | Connect these pins to a 0.8-V power supply. |
| VCCBAT | Power | Battery back-up power supply for device security Advanced Encryption Standard, battery-backed RAM (AES BBRAM) key register. | When using the device security AES BBRAM key, connect this pin to a non-volatile battery power source in the range of 1.0 V – 1.8 V. A series RC (R=10 kΩ, C=1µF) circuit must be added to the VCCBAT rail. Connect a 10 kΩ resistor in series between the battery power source and VCCBAT. You must also connect a 1µF capacitor between VCCBAT and ground. For more information about the schematic diagram, refer to AN 910: Agilex™ 7 Power Distribution Network Design Guidelines . Provide a minimum decoupling of 47 nF for the VCCBAT power rail near the VCCBAT pin. When not using the AES BBRAM key, tie this pin to ground. |
| VCCPLL_SDM | Power | VCCPLL_SDM supplies analog power to the SDM block PLLs. | With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT. Decoupling for these pins depends on the design decoupling requirements of the specific board. |
| GND | Ground | Device ground pins. | Connect all GND pins to the board ground plane. |
| VREFB[2][AN0,BN0,CN0,DN0,EN0,FN0] VREFB[3][AN0,BN0,CN0,DN0,EN0,FN0] |
Power | Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then use these pins as voltage-reference pins for the bank. For more information about the supported pins, refer to the device pin-out file. |
If VREF pins are not used, connect them to GND. |
| VCCLSENSE | Output | Differential sense line to external regulator. | VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect your regulator's differential remote sense lines to the respective VCCLSENSE and GNDSENSE pins, and refer to the design recommendations of the regulator's vendor on your board. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source. You must connect the VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs. |
| GNDSENSE | |||
| VCCADC | Power | ADC power pin for the voltage sensors. | You must supply a low noise 1.8-V power supply to this pin if you are using the internal voltage sensors of the Agilex™ 7 device. Tie this pin to VCCPT with proper isolation filtering. |
| VCCFUSEWR_SDM | Power | The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ 7 security architecture. | A 1.8-V power supply is required on this pin if field-programming of the eFuses is required. In addition, Altera recommends connecting a regulator with 1.8-V output to allow access to enhanced configuration and security debug tools. If you choose not to power this pin, tie it to VCCIO_SDM. Do not leave this pin floating or tied to GND. |