Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.2.3. Optional/Dual-Purpose Configuration Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Attention: There are pins usage restriction for the dual-purpose pins in the Avalon® streaming x16 and x32 modes. For more information, refer to the Enabling Dual-Purpose Pins section in the Agilex™ 7 Configuration User Guide .
Table 4.  Optional/Dual-Purpose Configuration Pins
Pin Name Pin Functions Pin Description Connection Guidelines
AVST_DATA[31:0] I/O, Input

Dual-purpose configuration data input pins.

Use AVST_DATA[15:0] pins for Avalon® Streaming Interface x16 mode, AVST_DATA [31:0] pins for Avalon® streaming x32 mode, or as regular I/O pins.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

Attention: Access to the I/O pins located in bank 3A with pin index[91...95] is not allowed for the Avalon® streaming x16 or x32 configuration scheme. You must leave these pins unconnected. For more information, refer to the device pin mapping files to identify the exact pin location.
If these pins are not used as the dual-purpose pins and they are not used as I/O pins, leave these pins unconnected.
AVST_READY(3A bank) I/O, Output

Dual-purpose Avalon® Streaming Interface data ready output pin. This pin is used for the Avalon® streaming x16 and x32 configuration schemes.

This pin cannot be used as a user I/O pin if you are using the Avalon® streaming x16 or x32 configuration scheme.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

Connect this pin to the ready signal input of the external configuration controller when configuring using the Avalon® streaming x16 or x32 interface.
AVST_CLK(3A bank) I/O, Input

Dual-purpose Avalon® Streaming Interface clock input pin. This pin is used for the Avalon® streaming x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

Connect this pin to the clock signal of the external configuration controller when configuring using the Avalon® streaming x16 or x32 interface.

Connect unused pins as defined in the Quartus® Prime software.

AVST_VALID(3A bank) I/O, Input

Dual-purpose configuration data valid pin. This pin is used for the Avalon® streaming x16 and x32 configuration schemes.

This pin can also be used as a user I/O pin after configuration.

This pin supports the 1.2-V LVCMOS I/O standard.

These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

Connect this pin to the data valid signal of the external configuration controller when configuring using the Avalon® streaming x16 or x32 interface.

Connect unused pins as defined in the Quartus® Prime software.

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