Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 11/25/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.7.1. HPS Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 22.  HPS Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCL_HPS Power VCCL_HPS supplies power to the HPS core.

For the range of the VCCL_HPS power supply voltage, refer to the Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series .

Speed Grade Power Supply Voltage (V)
VCC VCCL_HPS
–1 VID

VID or standalone 0.95 (performance boost option)
–2 VID VID
–3 VID VID
–4X VID 0.8
–4F 0.8 0.8

VCCL_HPS can be shared with VCC if they are at the same VID voltage level.

If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to the HPS power supply. Do not leave the VCCL_HPS floating or connected to GND.

VCCIO_HPS Power The HPS dedicated I/Os support 1.8-V voltage level.

Connect these pins to 1.8-V power supply. You have the option to source VCCIO_HPS pins from the same regulator as VCCIO_SDM.

If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to the HPS power supply. Do not leave the VCCIO_HPS floating or connected to GND.

VCCPLL_HPS Power VCCPLL_HPS supplies analog power to the HPS PLLs.

Connect these pins to a 1.8-V power supply. You have the option to share VCCPLL_HPS with the same regulator as VCCPLL_SDM.

If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to the HPS power supply. Do not leave the VCCPLL_HPS floating or connected to GND.

VCCPLLDIG_HPS Power Digital power supply of the PLL in HPS.

Connect this to the VCCL_HPS with proper isolation filtering.

If you do not intend to utilize the HPS in the Agilex™ 7 device, you must still provide power to the HPS power supply. Do not leave the VCCPLLDIG_HPS floating or connected to GND.

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