Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 6/12/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.7.5. HPS SDMMC Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 26.  HPS SDMMC Pins Altera recommends adding a 1-kΩ to 10-kΩ pull-up resistor to every SDMMC data signal that is used.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments (select from one of the groups)
Group 1 Group 2
SDMMC_CCLK SDMMC clock out. Output HPS_IOA_1 HPS_IOB_15
SDMMC_CMD

SDMMC command line.

Pull this pin high on the board with a weak pull-up resistor. For example, a 10-kΩ to VCCIO_HPS.

I/O HPS_IOA_2 HPS_IOB_14
SDMMC_DATA0 SDMMC Data 0. I/O HPS_IOA_3 HPS_IOB_13
SDMMC_DATA1 SDMMC Data 1. I/O HPS_IOA_4 HPS_IOB_16
SDMMC_DATA2 SDMMC Data 2. I/O HPS_IOA_5 HPS_IOB_17
SDMMC_DATA3

SDMMC Data 3.

When using SD card, there is an existing 50-kΩ pull-up on SDMMC Data Bit 3 which can be disabled in the HPS software by using the SET_CLR_CARD_DETECT (ACMD42) command. This is not applicable to the eMMC flash.

I/O HPS_IOA_6 HPS_IOB_18
SDMMC_DATA4 SDMMC Data 4. I/O HPS_IOA_7 HPS_IOB_19
SDMMC_DATA5 SDMMC Data 5. I/O HPS_IOA_8 HPS_IOB_20
SDMMC_DATA6 SDMMC Data 6. I/O HPS_IOA_9 HPS_IOB_21
SDMMC_DATA7 SDMMC Data 7. I/O HPS_IOA_10 HPS_IOB_22
SDMMC_PWR_EN SDMMC Power Enable. Output HPS_IOA_11 HPS_IOB_23
Level Two Title