Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

ID 683112
Date 6/12/2024
Public
Document Table of Contents

1.7.4. HPS GPIO Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 25.  HPS GPIO PinsThere are two GPIO controllers (GPIO0 and GPIO1) for the Agilex™ 7 HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
GPIO0_IO[0..23]

General purpose input output.

Ensure that the I/O standard used is compatible with VCCIO_HPS.

Supports 1.8 V LVCMOS I/O standard.

If you do not intend to utilize the HPS, these pins are in the tri-state mode with a weak pull-up enabled. Ensure that the weak high state of each pin does not cause issues with the external circuitry. If it might, isolate with a 0 Ω resistor that is depopulated on the board.

I/O

HPS_IOA_[1..24]

HPS_IOB_[1..24]

GPIO1_IO[0..23]