Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 6/12/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.4.2. P-Tile Transceiver Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 17.  P-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
GXP[L10A,L10C]_RX_CH[15:0][p,n] Input

PCIe* Gen4-based receiver pins, specific to the P-Tile transceivers on the left (L) side of the device.

For more information about the supported pins, refer to the device pin-out file.

When these pins are not used, they must be tied via a 1 kΩ pull-down resistor to GND.

GXP[L10A,L10C]_TX_CH[15:0][p,n] Output

PCIe* Gen4-based transmitter pins, specific to the P-Tile transceivers on the left (L) side of the device.

For more information about the supported pins, refer to the device pin-out file.

Transmitter pins must be AC coupled. The capacitor value ranges from 176 nF to 256 nF per PCIe* Gen4 specification.

When these pins are not used, they must be floating.
REFCLK_GXP[L10A,L10C]_CH[0,2][p,n] Input

Standard PCIe* HCSL reference clock input pins, specific to the P-Tile transceivers on the left (L) side of the device.

For more information about the supported pins, refer to the device pin-out file.

For HCSL I/O standard, it only supports DC coupling.

You must connect a 100-MHz reference clock to both reference clock inputs for x16 and 4x4 modes. These reference clocks must be derived from the same clock source. A fan-out buffer can be used but must meet a ± 300 ppm requirement.

For 2x8 modes, you must connect both reference clock inputs to the same clock source or connect to two independent clock sources.

If the P-Tile is completely unused, tie both REFCLK inputs to GND.

Unused reference clock pins must be tied to 1kΩ pull-down resistor to GND.

IO_AUX_RREF[10,12]_P Input

Reference resistor for the Embedded Multi-Die-Interconnect Bridge (EMIB) of the P-Tile transceivers.

Not all pins are available in each device density and package combination. For more information, refer to the specific device pin-out file.

Connect each IO_AUX_RREF to a 2.8 kΩ resistor (±1%) to GND.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.
U[10,12]_P_IO_RESREF_0 Input

Transceiver reference resistor connection for PMA circuitry to provide termination for calibration.

Not all pins are available in each device density and package combination. For more information, refer to the specific device pin-out file.

Connect each pin to a 169 Ω 1% (100 ppm/°C) precision resistor to GND.

Place this resistor very close to the IO_RESREF pin. Avoid routing any noisy signals next to this reference resistor or its traces. Tie resistor to GND plane through a via placed very close to the reference resistor.

External reference resistor parasitic capacitance load must be less than 14 pF. Maximum parasitic capacitance includes external loading of PHY count, package trace, and PCB trace. Each PHY connected to the IO_RESREF pin adds an additional 1.5 pF of loading.

I_PIN_PERST_N_U[10,12]_P Input

PCI Express* ( PCIe* ) Platform reset pin.

For more information about the supported pins, refer to the device pin-out file.

In a PCI Express* ( PCIe* ) adapter card implementation, connect the PCIe* nPERST signal from the PCIe* edge connector to each P-Tile transceiver bank I_PIN_PERST_N input.

Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V I_PIN_PERST_N input of each P-Tile transceiver that is used on the board.

Provide a 1.8-V pull-up resistor to the I_PIN_PERST_N input as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

If the tile is unused, tie to GND.

In cases where two independent clock sources are used for 2x8 bifurcation mode, ensure I_PIN_PERST_N be deasserted high after both reference clocks are stable.

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