Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

ID 683112
Date 6/12/2024
Public
Document Table of Contents

1.4. Agilex™ 7 P-Tile Pins

This section contains connection guidelines that are specific to the Agilex™ 7 P-tile devices. The connection guidelines for the Agilex™ 7 core pins are listed in the Agilex™ 7 Core Pins section.
Note: You cannot change the P-tile IP for the PCI Express (PCIe) pin allocation in the Quartus® Prime project, but the P-tile IP for the PCIe supports lane reversal and polarity inversion on the PCB.