Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 6/12/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.5.2. F-Tile Transceiver Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 19.  F-Tile Transceiver Pins
Pin Name Pin Functions Pin Description Connection Guidelines
RCOMP_P_FHT_GXF Input External biasing resistor for F-Tile FHT.

Connect each RCOMP_P_FHT_GXF pin with a 1.5-KΩ resistor (0.1%) to the RCOMP_N_FHT_GXF pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 1.5-KΩ resistor between the RCOMP_P_FHT_GXF and RCOMP_N_FHT_GXF pins.

RCOMP_N_FHT_GXF
RCOMP_P_Q2_CH1_FGT_GXF Input External biasing resistor for F-Tile FGT.

Connect each RCOMP_P_Q2_CH1_FGT_GXF pin with a 499-Ω resistor (0.1%) to the RCOMP_N_Q2_CH1_FGT_GXF pin.

In the PCB layout, the trace from this pin to the resistor needs to be routed such that it avoids any aggressor signals.

If this tile is unused, you must connect the 499-Ω resistor between the RCOMP_P_Q2_CH1_FGT_GXF and RCOMP_N_Q2_CH1_FGT_GXF pins.

RCOMP_N_Q2_CH1_FGT_GXF
REFCLK_FHT[L,R]_CH[0,1]P Input

F-Tile FHT reference clock input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

REFCLK_FHT[L,R]_CH[0,1]N
REFCLK_FGT[L,R]_Q[0,1,2,3]_RX_CH[0,1,2,3,4,5,6,7]P Input

F-Tile FGT reference clock input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling case.

Tie to GND if these pins are not used.

REFCLK_FGT[L,R]_Q[0,1,2,3]_RX_CH[0,1,2,3,4,5,6,7]N
REFCLK_FGT[L,R]_Q[2,3]_CH[8,9]P Input/Output

F-Tile FGT reference clock input or recovery clock output pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled. Clock driver must be compatible with input requirement in DC coupling input case.

Tie to GND or leave floating if this tile is not used. Tie to GND if the tile is used, and the pin is not used.

REFCLK_FGT[L,R]_Q[2,3]_CH[8,9]N
FHT[L,R]_RX_CH[0,1,2,3]P Input

F-Tile FHT transceiver input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

If unused, Altera recommends you to tie it to GND, but you have the option to leave it floating.

FHT[L,R]_RX_CH[0,1,2,3]N
FHT[L,R]_TX_CH[0,1,2,3]P Output

F-Tile FHT transceiver output pins.

For more information about the supported pins, refer to the device pin-out file.

 Leave unused pins floating.
FHT[L,R]_TX_CH[0,1,2,3]N
FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]P Input

F-Tile FGT transceiver input pins.

For more information about the supported pins, refer to the device pin-out file.

AC or DC coupled.

If unused, Altera recommends you to tie it to GND, but you have the option to leave it floating.

The F-Tile PCI Express* hard IP supports x2 or x1 link width configuration via link downtraining from x4. For these two cases, leave the unused upper lanes unconnected on the PCB and do not tie them to GND.

FGT[L,R]_RX_Q[0,1,2,3]_CH[0,1,2,3]N
FGT[L,R]_TX_Q[0,1,2,3]_CH[0,1,2,3]P Output

F-Tile FGT transceiver output pins.

For more information about the supported pins, refer to the device pin-out file.

 Leave unused pins floating.
FGT[L,R]_TX_Q[0,1,2,3]_CH[0,1,2,3]N
I_PIN_PERST_N_GXF Input External reset for F-Tile in one PCIe* case.

1.8-V LVCMOS reset input in PCIe* case.

In a PCIe* adapter card implementation, connect this signal from the PCIe* edge connector to each F-Tile PCIe* reset input pin. Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V input of each F-Tile transceiver that is used on the board. Provide a 1.8-V pull-up resistor for this input pin as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

If the F-Tile is unused, or the F-Tile is used but PCI Express* is unused, tie to GND.

In case one reset pin controls multiple PCIe* IPs in bifurcation mode, ensure that this signal is de-asserted high after all IPs reference clocks are stable.

ENB_GXF_FHT Input Enable or disable FHT support in F-Tile. Tie to VCCCLK_GXF if FHT channels are used; tie to GND if FHT channel is not used.
APROBE_GXF_FGT[12A,12B,12C,13A,13B,13C]_Q[0,2,3]_CH3 — — Leave these pins floating.
APROBE2_GXF_FGT[12A,12B,12C,13A,13B,13C]_Q3_CH3 — — Leave these pins floating.
APROBE1_GXF_FHT[12A,12B,12C,13A,13B,13C] — — Leave these pins floating.
APROBE2_GXF_FHT[12A,12B,12C,13A,13B,13C] — — Leave these pins floating.
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