Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

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ID 683112
Date 6/12/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series x
1.1. Pins Status for Agilex™ 7 F-Series and I-Series Devices 1.2. Agilex™ 7 FPGA Core Pins 1.3. Agilex™ 7 E-Tile Pins 1.4. Agilex™ 7 P-Tile Pins 1.5. Agilex™ 7 F-Tile Pins 1.6. Agilex™ 7 R-Tile Pins 1.7. Agilex™ 7 Hard Processor System (HPS) Pins 1.8. Agilex™ 7 Power Supply Sharing Guidelines 1.9. Notes to Agilex™ 7 F-Series and I-Series Device Family Pin Connection Guidelines 1.10. Document Revision History for the Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series
1.2. Agilex™ 7 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. No Connect and DNU Pins 1.2.10. Power Supply Pins 1.2.11. Secure Device Manager (SDM) Pins 1.2.12. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 7 E-Tile Pins x
1.3.1. E-Tile Power Supply Pins 1.3.2. E-Tile Transceiver Pins
1.4. Agilex™ 7 P-Tile Pins x
1.4.1. P-Tile Power Supply Pins 1.4.2. P-Tile Transceiver Pins
1.5. Agilex™ 7 F-Tile Pins x
1.5.1. F-Tile Power Supply Pins 1.5.2. F-Tile Transceiver Pins
1.6. Agilex™ 7 R-Tile Pins x
1.6.1. R-Tile Power Supply Pins 1.6.2. Agilex™ 7 R-Tile Transceiver Pins
1.7. Agilex™ 7 Hard Processor System (HPS) Pins x
1.7.1. HPS Supply Pins 1.7.2. HPS Oscillator Clock Input Pin 1.7.3. HPS JTAG Pins 1.7.4. HPS GPIO Pins 1.7.5. HPS SDMMC Pins 1.7.6. HPS NAND Pins 1.7.7. HPS USB Pins 1.7.8. HPS EMAC Pins 1.7.9. HPS I2C_EMAC and MDIO Pins 1.7.10. HPS I2C Pins 1.7.11. HPS SPI Pins 1.7.12. HPS UART Pins 1.7.13. HPS Trace Pins
1.8. Agilex™ 7 Power Supply Sharing Guidelines x
1.8.1. Example 1— Agilex™ 7 Devices (P-Tile and E-Tile) 1.8.2. Example 2— Agilex™ 7 Devices (F-Tile and R-Tile)
1. Agilex™ 7 Device Family Pin Connection Guidelines: F-Series and I-Series

1.3.1. E-Tile Power Supply Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 14.  E-Tile Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCH_GXE[R1] Power Analog power, block level transmitter buffers for E-Tile, specific to the right (R) side of the device.

Connect VCCH_GXE to a 1.1-V low noise switching regulator.

VCCH_GXE must be powered up even when the E-Tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines .

VCCRT_GXE[R1] Power Analog power, used for the high-speed circuitry for the E-Tile, specific to the right (R) side of the device.

VCCRT_GXE can be connected to a 0.9-V low noise switching regulator.

You must connect VCCRT_GXE to VCCH through an LC filter. For more information about the LC filter design, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines .

VCCRT_GXE must be powered up even when the E-Tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines .

VCCRTPLL_GXE[R1] Power Analog power, used for the high-speed circuitry for the E-Tile, specific to the right (R) side of the device.

You must source the VCCRTPLL_GXE from the VCCH with proper isolation filtering.

Filtering may be optional if this voltage rail can meet the noise mask requirement. For more information about the noise mask requirements, refer to the Agilex™ 7 Power Management User Guide.

VCCRTPLL_GXE must be powered up even when the E-Tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines .

VCCCLK_GXE[R1] Power I/O power, specific to the E-Tile reference clock buffers.

Connect VCCCLK_GXE to a 2.5-V low noise switching regulator.

VCCCLK_GXE must be powered up even when the E-Tile transceivers are not used.

For more details about the decoupling recommendations for this voltage rail, refer to the AN 910: Agilex™ 7 Power Distribution Network Design Guidelines .

VCC_HSSI_GXE[R1] Power Primary digital supply for all digital signals, specific to E-Tile.

Connect VCC_HSSI_GXE to a 0.9-V low noise switching regulator. This voltage rail must be shared with VCCH.

VCC_HSSI_GXE must be powered up even when the E-Tile transceivers are not used.

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