L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.10.7. Secondary PCI Express Extended Capability Header

Table 79.  Secondary PCI Express Extended Capability Header - 0x188

Bits

Register Description

Default Value

Access

[15:0]

PCI Express Extended Capability ID.

0x0019

RO

[19:16]

Capability Version.

0x1

RO

[31:20] Next Capability Pointer. The following values are possible:
  • If TPH Requester Capability is supported by the Function, its Next Capability = TPH Requester, 0x1FC.
  • Otherwise, if the ATS Capability is supported by the Function, its Next Capability = ATS, 0x284.
  • In all other cases: Next Capability = 0.
0x1FC, 0x284, or 0 RO