L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public

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6.1.18. Power Management Interface

Software programs the Device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The IP core supports the required PCI D0 and D3 Power Management states. D1 and D2 states are not supported.
Table 47.  Power Management Interface Signals

Signal

Direction

Description

pm_linkst_in_l1

Output

When asserted, indicates that the link is in the L1 state.

pm_linkst_in_l0s

Output

When asserted, indicates that the link is in the L0s state.

pm_state[2:0]

Output

Specifies the current power state.

pm_dstate[2:0]

Output

Specifies the power management D-state for PF0.

apps_pm_xmt_pme

Input

Wake Up. The Application Layer asserts this signal for 1 cycle to wake up the Power Management Capability (P MC) state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a PM_PME Message. This port is functionally identical to outband_pwrup_cmd. You can use this signal or outband_pwrup_cmd to request a return from a low-power state to D0.

apps_ready_entr_l23 Input

The application logic asserts this signal to indicate that it is ready to enter the L2/L3 Ready state. The apps_ready_entr_l23 signal is provided for applications that must control the L2/L3 Ready entry (in case certain tasks must be performed before going into L2/L3 Ready). The core delays sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes active.

This is a level-sensitive signal.

apps_pm_xmt_turnoff

Input

Application Layer request to generate a PM_Turn_Off message. The Application Layer must assert this signal for one clock cycle. The IP core does not return an acknowledgment or grant signal. The Application Layer must not pulse this signal again until the previous message has been transmitted.

app_init_rst

Input

Application Layer request for a hot reset to downstream devices.

app_xfer_pending Input When asserted, prevents the IP core from entering L1 state or initiates exit from the L1 state.