Visible to Intel only — GUID: lbl1465329199412
Ixiasoft
Visible to Intel only — GUID: lbl1465329199412
Ixiasoft
6.1.11. Resets
The reset logic requires a free running clock that is stable and available to the IP core at configuration time.
Signal |
Direction |
Description |
---|---|---|
currentspeed[1:0] | Output | Indicates the current speed of the PCIe module. The following encodings are defined:
|
npor | Input |
The Application Layer drives this active low reset signal. npor resets the entire IP core, PCS, PMA, and PLLs. npor should be held for a minimum of 20 ns. Gen3 x16 variants, should hold npor for at least 10 cycles. This signal is edge, not level sensitive; consequently, a low value on this signal does not hold custom logic in reset. This signal cannot be disabled. |
pin_perst | Input |
Active low reset from the PCIe reset pin of the device. Resets the datapath and control registers. |
ninit_done | Input | This is an active-low asynchronous input. A "1" on this signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Avalon® streaming IP for PCIe. For more details on how to use this input, refer to Including the Reset Release Intel® FPGA IP in Your Design. |
pld_clk_inuse |
Output | This reset signal has the same effect as reset_status. This signal is provided for backwards compatibility with Arria® 10 devices. |
pld_core_ready |
Input | When asserted, indicates that the Application Layer is ready. The IP core can releases reset after this signal is asserted. |
reset_status |
Output | Active high reset status. When high, indicates that the IP core is not ready for usermode. reset_status is deasserted only when npor is deasserted and the IP core is not in reset. Use reset_status to drive the reset of your application. Synchronous to coreclkout_hip. |
clr_st |
Output | clr_st has the same functionality as reset_status. It is provided for backwards compatibility with previous device families. |
serdes_pll_locked |
Output | When asserted, indicates that the PLL that generates coreclkout_hip is locked. In pipe simulation mode this signal is always asserted. |