L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public

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6.1.2.2. Avalon-ST RX Interface rx_st_ready Deasserts for the 256-Bit Interface

This timing diagram illustrates the timing of the RX interface when the application throttles the Intel L-/H-Tile Avalon-ST for PCI Express IP by deasserting rx_st_ready. The rx_st_valid signal deasserts within 17 cycles of the rx_st_ready deassertion for variants other than the Gen3 x16 variant, and within 18 cycles for the Gen3 x16 variant. The rx_st_valid signal reasserts within 17 cycles after rx_st_ready reasserts if there is more data to send for variants other than the Gen3 x16 variant, and within 18 cycles for the Gen3 x16 variant. rx_st_data is held until the application is able to accept it.

Avalon-ST RX Interface rx_st_valid Reasserts for the 256-Bit Interface

To achieve the best throughput, Intel recommends that you size the RX buffer in your application logic to avoid the deassertion of rx_st_ready.
Figure 37. Avalon-ST RX Interface rx_st_valid Deasserts for the 256-Bit Interface
Figure 38.