L- and H-tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 3/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.3. PCI Express Capability Structures

The layout of the most basic Capability Structures are provided below. Refer to the PCI Express Base Specification for more information about these registers.
Figure 63. Power Management Capability Structure - Byte Address Offsets and Layout
Figure 64. MSI Capability Structure
Figure 65. PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, registers that are not applicable to a device are reserved.
Figure 66. MSI-X Capability Structure
Figure 67. PCI Express AER Extended Capability Structure
Note: Refer to the Advanced Error Reporting Capability section for more details about the PCI Express AER Extended Capability Structure.