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1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Interrupts
8. Registers
9. Testbench and Design Example
10. Troubleshooting and Observing the Link
A. PCI Express Core Architecture
B. TX Credit Adjustment Sample Code
C. Root Port Enumeration
D. Document Revision History
1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Recommended Fabric Speed Grades
1.6. Performance and Resource Utilization
1.7. Transceiver Tiles
1.8. PCI Express IP Core Package Layout
1.9. Channel Availability
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
3.1. Avalon-ST RX Interface
3.2. Avalon-ST TX Interface
3.3. TX Credit Interface
3.4. TX and RX Serial Data
3.5. Clocks
3.6. Function-Level Reset (FLR) Interface
3.7. Control Shadow Interface for SR-IOV
3.8. Configuration Extension Bus Interface
3.9. Hard IP Reconfiguration Interface
3.10. Interrupt Interfaces
3.11. Power Management Interface
3.12. Reset
3.13. Transaction Layer Configuration Interface
3.14. PLL Reconfiguration Interface
3.15. PIPE Interface (Simulation Only)
4.1. Stratix 10 Avalon-ST Settings
4.2. Multifunction and SR-IOV System Settings
4.3. Base Address Registers
4.4. Device Identification Registers
4.5. TPH/ATS Capabilities
4.6. PCI Express and PCI Capabilities Parameters
4.7. Configuration, Debug and Extension Options
4.8. PHY Characteristics
4.9. Example Designs
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces
6.1.2. Avalon-ST 256-Bit RX Interface
6.1.3. Avalon-ST 512-Bit RX Interface
6.1.4. Avalon-ST 256-Bit TX Interface
6.1.5. Avalon-ST 512-Bit TX Interface
6.1.6. TX Credit Interface
6.1.7. Interpreting the TX Credit Interface
6.1.8. Clocks
6.1.9. Update Flow Control Timer and Credit Release
6.1.10. Function-Level Reset (FLR) Interface
6.1.11. Resets
6.1.12. Interrupts
6.1.13. Control Shadow Interface for SR-IOV
6.1.14. Transaction Layer Configuration Space Interface
6.1.15. Configuration Extension Bus Interface
6.1.16. Hard IP Status Interface
6.1.17. Hard IP Reconfiguration
6.1.18. Power Management Interface
6.1.19. Serial Data Interface
6.1.20. PIPE Interface
6.1.21. Test Interface
6.1.22. PLL IP Reconfiguration
6.1.23. Message Handling
8.1.1. Register Access Definitions
8.1.2. PCI Configuration Header Registers
8.1.3. PCI Express Capability Structures
8.1.4. Intel Defined VSEC Capability Header
8.1.5. General Purpose Control and Status Register
8.1.6. Uncorrectable Internal Error Status Register
8.1.7. Uncorrectable Internal Error Mask Register
8.1.8. Correctable Internal Error Status Register
8.1.9. Correctable Internal Error Mask Register
8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map
8.1.10.1. ARI Enhanced Capability Header
8.1.10.2. SR-IOV Enhanced Capability Registers
8.1.10.3. Initial VFs and Total VFs Registers
8.1.10.4. VF Device ID Register
8.1.10.5. Page Size Registers
8.1.10.6. VF Base Address Registers (BARs) 0-5
8.1.10.7. Secondary PCI Express Extended Capability Header
8.1.10.8. Lane Status Registers
8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header
8.1.10.10. TPH Requester Capability Register
8.1.10.11. TPH Requester Control Register
8.1.10.12. Address Translation Services ATS Enhanced Capability Header
8.1.10.13. ATS Capability Register and ATS Control Register
9.4.1. ebfm_barwr Procedure
9.4.2. ebfm_barwr_imm Procedure
9.4.3. ebfm_barrd_wait Procedure
9.4.4. ebfm_barrd_nowt Procedure
9.4.5. ebfm_cfgwr_imm_wait Procedure
9.4.6. ebfm_cfgwr_imm_nowt Procedure
9.4.7. ebfm_cfgrd_wait Procedure
9.4.8. ebfm_cfgrd_nowt Procedure
9.4.9. BFM Configuration Procedures
9.4.10. BFM Shared Memory Access Procedures
9.4.11. BFM Log and Message Procedures
9.4.12. Verilog HDL Formatting Functions
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10.2.1.2. Launching the PCIe* Link Inspector
Use the design example you compiled in the Quick Start Guide, to familiarize yourself with the PCIe* Link Inspector. Follow the steps in the Generating the Avalon® -ST Design or Generating the Avalon® -MM Design and Compiling the Design to generate the SRAM Object File, (.sof) for this design example.
To use the PCIe* Link Inspector, download the .sof to the Intel® Stratix® 10 Development Kit. Then, open the System Console on the test PC and load the design to the System Console as well. Loading the .sof to the System Console allows the System Console to communicate with the design using NPDME. NPDME is a JTAG-based Avalon® -MM master. It drives an Avalon® -MM slave interfaces in the PCIe* design. When using NPDME, the Intel® Quartus® Prime software inserts the debug interconnect fabric to connect with JTAG.
Here are the steps to complete these tasks:
- Use the Intel® Quartus® Prime Programmer to download the .sof to the Intel® Stratix® 10 FPGA Development Kit.
Note: To ensure that you have the correct operation, you must use the same version of the Intel® Quartus® Prime Programmer and Intel® Quartus® Prime Pro Edition software that you used to generate the .sof.
- To load the design to the System Console:
- Launch the Intel® Quartus® Prime Pro Edition software on the test PC.
- Start the System Console, Tools > System Debugging Tools > System Console.
- On the System Console File menu, select Load design and browse to the .sof file.
- Select the .sof and click OK.
The .sof loads to the System Console.
- In the System Console Tcl console, type the following commands:
% cd <project_dir>/ip/pcie_example_design/ pcie_example_design_DUT/altera_pcie_s10_hip_ast_<version>/synth/altera_pcie_s10_link_inspector % source TCL/setup_adme.tcl % source TCL/xcvr_pll_test_suite.tcl % source TCL/pcie_link_inspector.tcl
The source TCL/pcie_link_inspector.tcl command automatically outputs the current status of the PCIe* link to the Tcl Console. The command also loads all the PCIe* Link Inspector functionality.
Figure 80. Using the Tcl Console to Access the PCIe* Link Inspector
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