Visible to Intel only — GUID: kmn1524129486766
Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
Visible to Intel only — GUID: kmn1524129486766
Ixiasoft
7.4.1. Test Case
The simulation test case performs the following steps:
- Starts up the example design with an operating speed of 10G.
- Configures the MAC, PHY, and FIFO buffer for both channels.
- Waits until the design example asserts the channel_tx_ready and channel_rx_ready signals for both channels.
- Sends the following packets:
- 64-byte packet
- 1518-byte packet
- 100-byte packet
- Repeats steps 2 to 7 for 10M, 100M, 1G, 2.5G, and 5G.
When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon® streaming interface of channel 0 received all packets successfully, all statistics error counters are zero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.
Figure 60. Sample Simulation Output