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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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9.2. Low Latency Ethernet 10G MAC
This topic lists the byte offsets the MAC registers.
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x2008 | RW | primary_mac_addr0 | 0x0 |
0x200C | RW | primary_mac_addr1 | 0x0 |
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x4000 | RW | tx_packet_control | 0x0 |
0x4004 | RO | tx_packet_status | 0x0 |
0x4100 | RW | tx_pad_control | 0x1 |
0x4200 | RW | tx_crc_control | 0x3 |
0x4400 | RW | tx_preamble_control | 0x0 |
0x6004 | RW | tx_frame_maxlength | 0x5EE(1518) |
0x4300 | RO | tx_underflow_counter0 | 0x0 |
0x4304 | RO | tx_underflow_counter1 | 0x0 |
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x4500 | RW | tx_pauseframe_control | 0x0 |
0x4504 | RW | tx_pauseframe_quanta | 0x0 |
0x4508 | RW | tx_pauseframe_enable | 0x1 |
0x4680 | RW | tx_pfc_priority_enable | 0x0 |
0x4600 | RW | pfc_pause_quanta_0 | 0x0 |
0x4604 | RW | pfc_pause_quanta_1 | 0x0 |
0x4608 | RW | pfc_pause_quanta_2 | 0x0 |
0x460C | RW | pfc_pause_quanta_3 | 0x0 |
0x4610 | RW | pfc_pause_quanta_4 | 0x0 |
0x4614 | RW | pfc_pause_quanta_5 | 0x0 |
0x4618 | RW | pfc_pause_quanta_6 | 0x0 |
0x461C | RW | pfc_pause_quanta_7 | 0x0 |
0x4640 | RW | pfc_holdoff_quanta_0 | 0x1 |
0x4644 | RW | pfc_holdoff_quanta_1 | 0x1 |
0x4648 | RW | pfc_holdoff_quanta_2 | 0x1 |
0x464C | RW | pfc_holdoff_quanta_3 | 0x1 |
0x4650 | RW | pfc_holdoff_quanta_4 | 0x1 |
0x4654 | RW | pfc_holdoff_quanta_5 | 0x1 |
0x4658 | RW | pfc_holdoff_quanta_6 | 0x1 |
0x465C | RW | pfc_holdoff_quanta_7 | 0x1 |
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x0000 | RW | rx_transfer_control | 0x0 |
0x0004 | RO | rx_transfer_status | 0x0 |
0x0100 | RW | rx_padcrc_control | 0x1 |
0x0200 | RW | rx_crccheck_control | 0x2 |
0x0400 | RW | rx_custom_preamble_forward | 0x0 |
0x0500 | RW | rx_preamble_control | 0x0 |
0x2000 | RW | rx_frame_control | 0x3 |
0x2004 | RW | rx_frame_maxlength | 1518 |
0x2010 | RW | rx_frame_spaddr0_0 | 0x0 |
0x2014 | RW | rx_frame_spaddr0_1 | 0x0 |
0x2018 | RW | rx_frame_spaddr1_0 | 0x0 |
0x201C | RW | rx_frame_spaddr1_1 | 0x0 |
0x2020 | RW | rx_frame_spaddr2_0 | 0x0 |
0x2024 | RW | rx_frame_spaddr2_1 | 0x0 |
0x2028 | RW | rx_frame_spaddr3_0 | 0x0 |
0x202C | RW | rx_frame_spaddr3_1 | 0x0 |
0x2060 | RW | rx_pfc_control | 0x1 |
0x0300 | RO | rx_pktovrflow_error | 0x0 |
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x4440 | RW | tx_period_10G | 0x33333 |
0x4448 | RW | tx_fns_adjustment_10G | 0x0 |
0x444C | RW | tx_ns_adjustment_10G | 0x0 |
0x4460 | RW | tx_period_mult_speed | 0x80000 |
0x4468 | RW | tx_fns_adjustment_mult_speed | 0x0 |
0x446C | RW | tx_ns_adjustment_mult_speed | 0x0 |
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x0440 | RW | rx_period_10G | 0x33333 |
0x0448 | RW | rx_fns_adjustment_10G | 0x0 |
0x044C | RW | rx_ns_adjustment_10G | 0x0 |
0x0460 | RW | rx_period_mult_speed | 0x80000 |
0x0468 | RW | rx_fns_adjustment_mult_speed | 0x0 |
0x046C | RW | rx_ns_adjustment_mult_speed | 0x0 |
Byte Offset | R/W | Name | HW Reset |
---|---|---|---|
0x7000 | RO | tx_stats_clr | 0x0 |
0x3000 | RO | rx_stats_clr | 0x0 |
0x7008:0x700C | RO | tx_stats_framesOK | 0x0 |
0x3008:0x300C | RO | rx_stats_framesOK | 0x0 |
0x7010:0x7014 | RO | tx_stats_framesErr | 0x0 |
0x3010:0x3014 | RO | rx_stats_framesErr | 0x0 |
0x7018:0x701C | RO | tx_stats_framesCRCErr | 0x0 |
0x3018:0x301C | RO | rx_stats_framesCRCErr | 0x0 |
0x7020:0x7024 | RO | tx_stats_octetsOK | 0x0 |
0x3020:0x3024 | RO | rx_stats_octetsOK | 0x0 |
0x7028:0x702C | RO | tx_stats_pauseMACCtrl_Frames | 0x0 |
0x3028:0x302C | RO | rx_stats_pauseMACCtrl_Frames | 0x0 |
0x7030:0x7034 | RO | tx_stats_ifErrors | 0x0 |
0x3030:0x3034 | RO | rx_stats_ifErrors | 0x0 |
0x7038:0x703C | RO | tx_stats_unicast_FramesOK | 0x0 |
0x3038:0x303C | RO | rx_stats_unicast_FramesOK | 0x0 |
0x7040:0x7044 | RO | tx_stats_unicast_FramesErr | 0x0 |
0x3040:0x3044 | RO | rx_stats_unicast_FramesErr | 0x0 |
0x7048:0x704C | RO | tx_stats_multicast_FramesOK | 0x0 |
0x3048:0x304C | RO | rx_stats_multicast_FramesOK | 0x0 |
0x7050:0x7054 | RO | tx_stats_multicast_FramesErr | 0x0 |
0x3050:0x3054 | RO | rx_stats_multicast_FramesErr | 0x0 |
0x7058:0x705C | RO | tx_stats_broadcast_FramesOK | 0x0 |
0x3058:0x305C | RO | rx_stats_broadcast_FramesOK | 0x0 |
0x7060:0x7064 | RO | tx_stats_broadcast_FramesErr | 0x0 |
0x3060:0x3064 | RO | rx_stats_broadcast_FramesErr | 0x0 |
0x7068:0x706C | RO | tx_stats_etherStatsOctets | 0x0 |
0x3068:0x306C | RO | rx_stats_etherStatsOctets | 0x0 |
0x7070:0x7074 | RO | tx_stats_etherStatsPkts | 0x0 |
0x3070:0x3074 | RO | rx_stats_etherStatsPkts | 0x0 |
0x7078:0x707C | RO | tx_stats_etherStatsUndersizePkts | 0x0 |
0x3078:0x307C | RO | rx_stats_etherStatsUndersizePkts | 0x0 |
0x7080:0x7084 | RO | tx_stats_etherStatsOversizePkts | 0x0 |
0x3080:0x3084 | RO | rx_stats_etherStatsOversizePkts | 0x0 |
0x7088:0x708C | RO | tx_stats_etherStatsPkts64Octets | 0x0 |
0x3088:0x308C | RO | rx_stats_etherStatsPkts64Octets | 0x0 |
0x7090:0x7094 | RO | tx_stats_etherStatsPkts65to127Octets | 0x0 |
0x3090:0x3094 | RO | rx_stats_etherStatsPkts65to127Octets | 0x0 |
0x7098:0x709C | RO | tx_stats_etherStatsPkts128to255Octets | 0x0 |
0x3098:0x309C | RO | rx_stats_etherStatsPkts128to255Octets | 0x0 |
0x70A0:0x70A4 | RO | tx_stats_etherStatsPkts256to511Octets | 0x0 |
0x30A0:0x30A4 | RO | rx_stats_etherStatsPkts256to511Octets | 0x0 |
0x70A8:0x70AC | RO | tx_stats_etherStatsPkts512to1023Octets | 0x0 |
0x30A8:0x30AC | RO | rx_stats_etherStatsPkts512to1023Octets | 0x0 |
0x70B0:0x70B4 | RO | tx_stats_etherStatPkts1024to1518Octets | 0x0 |
0x30B0:0x30B4 | RO | rx_stats_etherStatPkts1024to1518Octets | 0x0 |
0x70B8:0x70BC | RO | tx_stats_etherStatsPkts1519toXOctets | 0x0 |
0x30B8:0x30BC | RO | rx_stats_etherStatsPkts1519toXOctets | 0x0 |
0x70C0:0x70C4 | RO | tx_stats_etherStatsFragments | 0x0 |
0x30C0:0x30C4 | RO | rx_stats_etherStatsFragments | 0x0 |
0x70C8:0x70CC | RO | tx_stats_etherStatsJabbers | 0x0 |
0x30C8:0x30CC | RO | rx_stats_etherStatsJabbers | 0x0 |
0x70D0:0x70D4 | RO | tx_stats_etherStatsCRCErr | 0x0 |
0x30D0:0x30D4 | RO | rx_stats_etherStatsCRCErr | 0x0 |
0x70D8:0x70DC | RO | tx_stats_unicastMACCtrlFrames | 0x0 |
0x30D8:0x30DC | RO | rx_stats_unicastMACCtrlFrames | 0x0 |
0x70E0:0x70E4 | RO | tx_stats_multicastMACCtrlFrames | 0x0 |
0x30E0:0x30E4 | RO | rx_stats_multicastMACCtrlFrames | 0x0 |
0x70E8:0x70EC | RO | tx_stats_broadcastMACCtrlFrames | 0x0 |
0x30E8:0x30EC | RO | rx_stats_broadcastMACCtrlFrames | 0x0 |
0x70F0:0x70F4 | RO | tx_stats_PFCMACCtrlFrames | 0x0 |
0x30F0:0x30F4 | RO | rx_stats_PFCMACCtrlFrames | 0x0 |
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