Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

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ID 683063
Date 1/11/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices 3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices 4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices 5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices 6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices 8. Interface Signals Description 9. Configuration Registers Description 10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives 11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Testing the Design in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.4. Simulation x
2.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 2.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
2.5. Hardware Testing x
2.5.1. Test Cases 2.5.2. Signal Tap Debug Signals
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 3.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Cases 3.5.2. Signal Tap Debug Signals
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking and Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Cases 4.5.2. Signal Tap Debug Signals
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signal 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme 5.3.4. Partial Reconfiguration Ready
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature 5.4.2. Test Case—Design Example without the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme 6.3.4. Partial Reconfiguration Ready 6.3.5. Timing Constraints
6.5. Hardware Testing x
6.5.1. Test Procedure
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.4. Simulation x
7.4.1. Test Case
7.5. Hardware Testing x
7.5.1. Test Procedure
8. Interface Signals Description x
8.1. Clock and Reset Interface Signals 8.2. Avalon® Memory-Mapped Interface Signals 8.3. Avalon® Streaming Interface Signals 8.4. PHY Interface Signals 8.5. Status Interface 8.6. IEEE 1588v2 Timestamp Interface Signals 8.7. Packet Classifier Interface Signals 8.8. ToD Interface Signals
9. Configuration Registers Description x
9.1. Register Access Definition 9.2. Low Latency Ethernet 10G MAC 9.3. PHY 9.4. Transceiver Reconfiguration 9.5. TOD
9.3. PHY x
9.3.1. 1G/10G PHY 9.3.2. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide

8.3. Avalon® Streaming Interface Signals

Table 32.   Avalon® Streaming Interface Signals
Signal Direction Width Description
avalon_st_tx_startofpacket[] In [NUM_CHANNELS] Assert this signal to indicate the beginning of the TX data.
avalon_st_tx_endofpacket[] In [NUM_CHANNELS] Assert this signal to indicate the end of the TX data.
avalon_st_tx_valid[] In [NUM_CHANNELS] Assert this signal to indicate that avalon_st_tx_data[] and other signals on this interface are valid.
avalon_st_tx_ready[] Out [NUM_CHANNELS] When asserted, indicates that the MAC IP core is ready to accept data. The reset value of this signal is non-deterministic.
avalon_st_tx_error[] In [NUM_CHANNELS] Assert this signal to indicate that the current TX packet contains errors.
avalon_st_tx_data[][] In [NUM_CHANNELS][m]

TX data from the client.

m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32.

avalon_st_tx_empty[][] In [NUM_CHANNELS][m]

Use this signal to specify the number of empty bytes in the cycle that contain the end of the TX data.

m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2.

  • 0x0—All bytes are valid.
  • 0x1—The last byte is invalid.
  • 0x2—The last two bytes are invalid.
  • 0x3—The last three bytes are invalid.
avalon_st_rx_startofpacket[] Out [NUM_CHANNELS] When asserted, indicates the beginning of the RX data.
avalon_st_rx_endofpacket[] Out [NUM_CHANNELS] When asserted, indicates the end of the RX data.
avalon_st_rx_valid[] Out [NUM_CHANNELS] When asserted, indicates that the avalon_st_rx_ data[] signal and other signals on this interface are valid.
avalon_st_rx_ready[] In [NUM_CHANNELS] Assert this signal when the client is ready to accept data.
avalon_st_rx_error[][] Out [NUM_CHANNELS][6] When set to 1, the respective bits indicate an error type:
  • Bit 0—PHY error. For 10 Gbps, the data on xgmii_rx_data contains a control error character (FE). For 10 Mbps,100 Mbps,1 Gbps, gmii_rx_err or mii_rx_err is asserted.
  • Bit 1—CRC error. The computed CRC value differs from the received CRC.
  • Bit 2—Undersized frame. The receive frame length is less than 64 bytes.
  • Bit 3—Oversized frame. The receive frame length is more than MAX_FRAME_SIZE.
  • Bit 4—Payload length error. The actual frame payload length is different from the value in the length/type field.
  • Bit 5—Overflow error. The receive FIFO buffer is full while it is still receiving data from the MAC IP core.
avalon_st_rx_data[][] Out [NUM_CHANNELS][m]

RX data to the client.

m is 64 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 32.

avalon_st_rx_empty[][] Out [NUM_CHANNELS][m]

Contains the number of empty bytes during the cycle that contain the end of the RX data.

m is 3 when the Use legacy Avalon Streaming Interface parameter is selected. Otherwise, m is 2.

avalon_st_tx_status_valid[] Out [NUM_CHANNELS] When asserted, this signal qualifies the avalon_st_txstatus_data[] and avalon_st_txstatus_error[] signals.
avalon_st_tx_status_data[][] Out [NUM_CHANNELS][40] Contains information about the TX frame.
  • Bits 0 to 15—Payload length.
  • Bits 16 to 31—Packet length.
  • Bit 32—When set to 1, indicates a stacked VLAN frame.
  • Bit 33—When set to 1, indicates a VLAN frame.
  • Bit 34—When set to 1, indicates a control frame.
  • Bit 35—When set to 1, indicates a pause frame.
  • Bit 36—When set to 1, indicates a broadcast frame.
  • Bit 37—When set to 1, indicates a multicast frame.
  • Bit 38—When set to 1, indicates a unicast frame.
  • Bit 39—When set to 1, indicates a PFC frame.
avalon_st_tx_status_error[][] Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates the following error type in the RX frame.
  • Bit 0—Undersized frame.
  • Bit 1—Oversized frame.
  • Bit 2—Payload length error.
  • Bit 3—Unused.
  • Bit 4—Underflow.
  • Bit 5—Client error.
  • Bit 6—Unused.
The error status is invalid when an overflow occurs.
avalon_st_rxstatus_valid[] Out [NUM_CHANNELS]

When asserted, this signal qualifies the avalon_st_rxstatus_data[] and avalon_st_rxstatus_error[] signals.

The MAC IP core asserts this signal in the same clock cycle the avalon_st_rx_endofpacket signal is asserted.

avalon_st_rxstatus_data[][] Out [NUM_CHANNELS][40] Contains information about the RX frame.
  • Bits 0 to 15—Payload length.
  • Bits 16 to 31—Packet length.
  • Bit 32—When set to 1, indicates a stacked VLAN frame.
  • Bit 33—When set to 1, indicates a VLAN frame.
  • Bit 34—When set to 1, indicates a control frame.
  • Bit 35—When set to 1, indicates a pause frame.
  • Bit 36—When set to 1, indicates a broadcast frame.
  • Bit 37—When set to 1, indicates a multicast frame.
  • Bit 38—When set to 1, indicates a unicast frame.
  • Bit 39—When set to 1, indicates a PFC frame.
avalon_st_rxstatus_error[][] Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates the following error type in the RX frame.
  • Bit 0—Undersized frame.
  • Bit 1—Oversized frame.
  • Bit 2—Payload length error.
  • Bit 3—Unused.
  • Bit 4—Underflow.
  • Bit 5—Client error.
  • Bit 6—Unused.
The error status is invalid when an overflow occurs.
avalon_st_pause_data[][] In [NUM_CHANNELS][2] This signal takes effect when the register bits, tx_pauseframe_enable[2:1], are both set to the default value 0.

Set this signal to the following values to trigger the corresponding actions.

  • 0x0—Stops pause frame generation.
  • 0x1—Generates an XON pause frame.
  • 0x2—Generates an XOFF pause frame. The MAC IP core sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3—Reserved.
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