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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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2.3.1. Design Components
Component | Description | |
---|---|---|
LL 10GbE MAC |
The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
For the design example with the IEEE 1588v2 feature, the following additional parameters are configured:
|
|
PHY | The 1G/10G and 10GBASE-KR PHY Intel® Arria® 10 FPGA IP. The design example uses the 1G/10G IP variant. | |
Address decoder | Decodes the addresses of the components in each Ethernet channel. | |
Multi-channel address decoder | Decodes the addresses of the components used by all channels, such as the Master TOD module. | |
Reset controller | Synchronizes the reset of all design components. | |
Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP. Resets the transceiver. | |
PLL | Generates clocks for all design components. | |
ATX PLL | Generates a TX serial clock for the Intel® Arria® 10 10G transceiver. | |
fPLL | Generates a TX serial clock for the Intel® Arria® 10 1G transceiver. | |
MDIO | Provides an MDIO interface to the external PHY. | |
FIFO | The Avalon® streaming single-clock FIFO. Buffers the RX and TX data between the MAC IP and the client. The default depth is 512. To increase the depth of the FIFO, change the DC_FIFO_DEPTH and SC_FIFO_DEPTH parameter values from 512 to 2048, under altera_eth_fifo instance in <Example Design>/rtl/altera_eth_channel.sv. | |
Design Components for the IEEE 1588v2 Feature | ||
Master TOD | The master TOD for all channels. | |
TOD Sync | Synchronizes the Master TOD to all Local TODs. | |
Local TOD | The TOD for each channel. | |
Master Pulse Per Second | Returns pulse per second (pps) for all channels. | |
Pulse Per Second | Returns pulse per second (pps) for each channel. | |
PTP packet classifier | Decodes the packet type of incoming PTP packets and returns the decoded information to the LL 10GbE MAC Intel® FPGA IP. |