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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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8.1. Clock and Reset Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
mm_clk csr_clk |
In | 1 | 125-MHz configuration clock for the Avalon® memory-mapped interface. |
mac_clk |
In | 1 | 156.25-MHz configuration clock for the Avalon® streaming interface. |
refclk | In | 1 | 125-MHz reference clock for the TX PLLs. |
pll_ref_clk_1g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the TX PLL in 1G mode. Frequency is 125 MHz. |
pll_ref_clk_10g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the TX PLL in 10G mode. Frequency is 644.53125 MHz. |
cdr_ref_clk_1g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the RX PLL in 1G mode. Frequency is 125 MHz. |
cdr_ref_clk_10g[] | In | [NUM_UNSHARED_CHANNELS] | Reference clock for the RX PLL in 10G mode. Frequency is 644.53125 MHz. |
xgmii_clk | Out | [NUM_UNSHARED_CHANNELS] | Clock used for single data rate (SDR) XGMII TX and RX interface in between MAC and PHY. Whenever present, this clock is also used for Avalon® streaming interface. Frequency is 156.25 MHz. |
rx_pma_clkout | Out | 1 | CDR recovered clock. |
rx_recovered_clk | Out | [NUM_CHANNELS] | RX clock, recovered from the RX data. |
tx_xcvr_clk | Out | 1 | 322.265625-MHz clock for the TX datapath. |
rx_xcvr_clk | Out | 1 | 322.265625-MHz clock for the RX datapath. |
iopll_half_clk | Out | 1 | 161.133-MHz synchronous clock derived from ref_clk_clk. |
ref_clk_clk | In | 1 | 322.265625-MHz clock for the TX PLL. |
core_clk_312 | Out | 1 | 312.5-MHz clock for the fast domain. |
core_clk_156 | Out | 1 | 156.25-MHz clock for the slow domain. |
channel_reset_n | In | [NUM_CHANNELS] | Assert this asynchronous and active-low signal to reset individual Ethernet channel. This does not impact the components running at multi_channel level, for example, master TOD, master PPS, and fPLLs. |
master_reset_n | In | 1 | Assert this asynchronous and active-low signal to reset the whole design example. |
reset | In | 1 | Assert this asynchronous and active-high signal to reset the whole design example. |
csr_rst_n | In | 1 | Active-low reset signal for the Avalon® memory-mapped interface. |
tx_rst_n | In | 1 | Active-low reset signal for the TX datapath. |
rx_rst_n | In | 1 | Active-low reset signal for the RX datapath. |
tx_digitalreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY. |
rx_digitalreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY. |
tx_analogreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PMA TX portion of the transceiver PHY. |
rx_analogreset | In | [NUM_CHANNELS] | Asynchronous and active-high signal to reset PMA RX portion of the transceiver PHY. |