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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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9.5. TOD
Byte Offset | Name | Bits | Description | Access | HW Reset |
---|---|---|---|---|---|
0x0000 | SecondsH | [15:0] | The upper 16 bits of the second field. | RW | 0x0 |
[31:16] | Reserved. | — | — | ||
0x0004 | SecondsL | 32 | The lower 32 bits of the second field. | RW | 0x0 |
0x0008 | NanoSec | 30 | The nanosecond field. | RW | 0x0 |
0x0010 | Period | [15:0] | The time-of-day. The period in fractional nanosecond. | RW | n 4 |
[19:16] | The time-of-day. The period in nanosecond. | ||||
[31:20] | Reserved. | — | — | ||
0x0014 | AdjustPeriod | [15:0] | The offset adjustment period. The period in fractional nanosecond. | RW | 0x0 |
[19:16] | The offset adjustment period. The period in nanosecond. | ||||
[31:20] | Reserved. | — | — | ||
0x0018 | AdjustCount | [19:0] | The number of adjusted period in clock cycles. | RW | 0x0 |
[31:20] | Not used. | — | — |
4 The default value for the period depends on the frequency of the PHY speed. For example, if frequency is 125 MHz, the period is 8 ns (PERIOD_NS = 0x0008 and PERIOD_FNS = 0x0000).