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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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8.8. ToD Interface Signals
Signal | Direction | Width | Description |
---|---|---|---|
master_pulse_per_second | Out | 1 | Pulse per second (PPS) from the master PPS module. The signal stay asserted for 10 ms. |
start_tod_sync[] | In | [NUM_CHANNELS] | Use this signal to trigger the TOD synchronization process. The time of day of the local TOD is synchronized to the time of day of the master TOD. The synchronization process continues as long as this signal remains asserted. |
pulse_per_second_10g[] | Out | [NUM_CHANNELS] | PPS from the 10G PPS module of channel n. The signal stay asserted for 10 ms. |
pulse_per_second_1g[] | Out | [NUM_CHANNELS] | PPS from the 1G PPS module of channel n. The signal stay asserted for 10 ms. |