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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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1.3.2. Testbench
Figure 4. Block Diagram of the Testbench
Component | Description |
---|---|
Device under test (DUT) | The design example. |
Avalon® driver | Consists of Avalon® streaming master bus functional models (BFMs). This driver forms the TX and RX paths. The driver also provides access to the Avalon® memory-mapped interface of the DUT. |
Ethernet packet monitors | Monitor TX and RX datapaths, and display the frames in the simulator console. |