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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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7.5.1. Test Procedure
Follow these steps to test the design examples in hardware:
- Run the following command in the system console to enable PHY serial loopback on Channel 0:
SET_CHANNEL_BASE_ADDR 0
SETPHY_SERIAL_LLPBK
Note: This step is only required if you are using Intel® Arria® 10 GX SI Development Board rev E and above, and on Channel 0 only. - Run the following command in the system console to start the test.
TEST_EXT_LB <channel> <speed> <burst_size>
Example: TEST_EXT_LB 0 10G 80000000
Table 28. Command Parameters Parameter Valid Values Description channel 0, 1 The channel number to test. speed 10M, 100M, 1G, 2P5G, 5G, 10G The PHY speed. burst_size An integer value The number of packets to generate for the test. - When the test is completed, observe the output displayed. The following diagrams show excerpts of the output, which shows that the Ethernet packet monitor block receives the same number of packets generated without error, and the TX and RX statistics counters.
Figure 61. Sample Test Output—Ethernet Packet Monitor
Figure 62. Sample Test Output—Statistics Counters