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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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2.4. Simulation
The simulation test cases demonstrate how the channel speed and the configuration of the PHY are changed. These test cases use circular loopback on the total number of Ethernet channels. The following table describes the steps to change the speed and configuration.
Operation | Description |
---|---|
Configuring the PHY speed. | Upon reset, all ports are set to 10G. To change the PHY speed, set the PHY memory map to change to other modes: 10G SerDes Framer Interface (SFI), 1G1000Base-X or 1G/100M/10M SGMII. |
Changing the speed between 1 Gbps and 10Gbps in 1000BASE-X. | Write one of the following values to the PHY's register at address offset 0x12C0.
Example To set port 0 to 1000BASE-X: write_32 0x02_52C0 0x11 To set port 0 to auto-detection mode: write_32 0x02_52C0 0x01 |
Changing the speed between 1 Gbps, 100 Mbps, and 10 Mbps in SGMII. |
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Section Content
Test Case—Design Example with the IEEE 1588v2 Feature
Test Case—Design Example without the IEEE 1588v2 Feature
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