Visible to Intel only — GUID: nfa1441265125245
Ixiasoft
Visible to Intel only — GUID: nfa1441265125245
Ixiasoft
8.2. Avalon® Memory-Mapped Interface Signals
Signal | Direction | Description |
---|---|---|
write csr_mac_write csr_phy_write csr_rcfg_write csr_native_phy_rcfg_write csr_master_tod_write csr_mch_write |
In | Assert this signal to request a write. |
read csr_mac_read csr_phy_read csr_rcfg_read csr_native_phy_rcfg_read csr_master_tod_read csr_mch_read |
In | Assert this signal to request a read. |
address csr_mac_address csr_phy_address csr_rcfg_address csr_native_phy_rcfg_address csr_master_tod_address csr_mch_address |
In | Use this bus to specify the register address you want to read from or write to. |
writedata csr_mac_writedata csr_phy_writedata csr_rcfg_writedata csr_native_phy_rcfg_writedata csr_master_tod_writedata csr_mch_writedata |
In | Carries the data to be written to the specified register. |
readdata csr_mac_readdata csr_phy_readdata csr_rcfg_readdata csr_native_phy_rcfg_readdata csr_master_tod_readdata csr_mch_readdata |
Out | Carries the data read from the specified register. |
waitrequest csr_mac_waitrequest csr_phy_waitrequest csr_native_phy_rcfg_waitrequest csr_master_tod_waitrequest csr_mch_waitrequest |
Out | When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests. |