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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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6.2. Hardware and Software Requirements
Intel uses the following hardware and software to test the design example in a Linux system:
- Intel® Quartus® Prime Pro Edition software (Partial Reconfiguration Ready)
- ModelSim® -AE, ModelSim® -SE, NCSim (Verilog only), VCS, and Xcelium* ( Intel® Quartus® Prime Pro Edition only) simulators
- For hardware testing:
- Intel® Arria® 10 GX Signal Integrity Development Board (10AX115S4F45E3SGE3)
- Cables—SMA cable, SFP+, and fiber optic cable
Note: Partial Reconfiguration Ready feature is supported from Intel® Quartus® Prime Pro Edition software version 17.0 onwards.