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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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7.3.1. Design Components
Component | Description |
---|---|
LL 10GbE MAC | The Low Latency Ethernet 10G MAC Intel® FPGA IP with the following configuration:
|
PHY | The 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP with the following configuration:
|
Channel address decoder | Decodes the addresses of the components in each Ethernet channel, such as PHY and LL 10GbE MAC. |
Multi-channel address decoder | Decodes the addresses of the components used by all channels , such as the Master ToD module. |
Top address decoder | Decodes the addresses of the top-level components, such as the Traffic Controller. |
Transceiver Reset Controller | The Transceiver PHY Reset Controller Intel® FPGA IP . Resets the transceiver. |
ATX PLL | Generates a TX serial clock for the Intel® Arria® 10 10G transceiver. |
Core fPLL | Generates clocks for all design components. |