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1. Quick Start Guide
2. 10M/100M/1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
3. 1G/10G Ethernet Design Example for Intel® Arria® 10 Devices
4. 10GBASE-R Ethernet Design Example for Intel® Arria® 10 Devices
5. 1G/2.5G Ethernet Design Example for Intel® Arria® 10 Devices
6. 1G/2.5G/10G Ethernet Design Example for Intel® Arria® 10 Devices
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Arria® 10 Devices
8. Interface Signals Description
9. Configuration Registers Description
10. Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide Archives
11. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Arria® 10 FPGA IP Design Example User Guide
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2.5.2. Signal Tap Debug Signals
The Signal Tap file is included for debugging. By default, this feature is disabled. To enable it, set the following assignment as below:
set_global_assignment -name ENABLE_SIGNALTAP ON
Component | Module Name | Signal |
---|---|---|
Top-level design example | altera_eth_top |
|
Multi-channel wrapper | Design example without the IEEE 1588v2 feature: altera_eth_top.altera_eth_multi_channel Design example with the IEEE 1588v2 feature: altera_eth_top.altera_eth_multi_channel_1588 |
|
MAC IP | <n>.altera_eth_10g_mac 2 |
|
PHY | <n>.altera_eth_10gkr_phy 2 |
|
XGMII | <n>.altera_eth_10g_mac.alt_em10g32.alt_em10g32unit 2 |
|
GMII | <n>.altera_eth_10g_mac 2 |
|
MII | <n>.altera_eth_10g_mac 2 |
|
2 Replace n with:
- altera_eth_top.altera_eth_multi_channel.altera_eth_channel for the design example without the IEEE 1588v2 feature.
- altera_eth_top.altera_eth_multi_channel_1588.altera_eth_channel_1588 for the design example with the IEEE 1588v2 feature.